*panel_config = panel_config_defaults;
}
-static bool filter_modes_for_single_channel_workaround(struct dc *dc,
- struct dc_state *context)
-{
- // Filter 2K@240Hz+8K@24fps above combination timing if memory only has single dimm LPDDR
- if (dc->clk_mgr->bw_params->vram_type == 34 &&
- dc->clk_mgr->bw_params->num_channels < 2 &&
- context->stream_count > 1) {
- int total_phy_pix_clk = 0;
-
- for (int i = 0; i < context->stream_count; i++)
- if (context->res_ctx.pipe_ctx[i].stream)
- total_phy_pix_clk += context->res_ctx.pipe_ctx[i].stream->phy_pix_clk;
-
- if (total_phy_pix_clk >= (1148928+826260)) //2K@240Hz+8K@24fps
- return true;
- }
- return false;
-}
-
bool dcn314_validate_bandwidth(struct dc *dc,
struct dc_state *context,
bool fast_validate)
if (!pipes)
goto validate_fail;
- if (filter_modes_for_single_channel_workaround(dc, context))
- goto validate_fail;
-
DC_FP_START();
// do not support self refresh only
out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, false);