1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
4 ST Ethernet IPs are built around a Synopsys IP Core.
6 Copyright(C) 2007-2011 STMicroelectronics Ltd
9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
11 Documentation available at:
12 http://www.stlinux.com
14 https://bugzilla.stlinux.com/
15 *******************************************************************************/
17 #include <linux/clk.h>
18 #include <linux/kernel.h>
19 #include <linux/interrupt.h>
21 #include <linux/tcp.h>
22 #include <linux/skbuff.h>
23 #include <linux/ethtool.h>
24 #include <linux/if_ether.h>
25 #include <linux/crc32.h>
26 #include <linux/mii.h>
28 #include <linux/if_vlan.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/slab.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/prefetch.h>
33 #include <linux/pinctrl/consumer.h>
34 #ifdef CONFIG_DEBUG_FS
35 #include <linux/debugfs.h>
36 #include <linux/seq_file.h>
37 #endif /* CONFIG_DEBUG_FS */
38 #include <linux/net_tstamp.h>
39 #include <linux/phylink.h>
40 #include <linux/udp.h>
41 #include <linux/bpf_trace.h>
42 #include <net/page_pool/helpers.h>
43 #include <net/pkt_cls.h>
44 #include <net/xdp_sock_drv.h>
45 #include "stmmac_ptp.h"
47 #include "stmmac_xdp.h"
48 #include <linux/reset.h>
49 #include <linux/of_mdio.h>
50 #include "dwmac1000.h"
54 /* As long as the interface is active, we keep the timestamping counter enabled
55 * with fine resolution and binary rollover. This avoid non-monotonic behavior
56 * (clock jumps) when changing timestamping settings at runtime.
58 #define STMMAC_HWTS_ACTIVE (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | \
61 #define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16)
62 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
64 /* Module parameters */
66 static int watchdog = TX_TIMEO;
67 module_param(watchdog, int, 0644);
68 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
70 static int debug = -1;
71 module_param(debug, int, 0644);
72 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
74 static int phyaddr = -1;
75 module_param(phyaddr, int, 0444);
76 MODULE_PARM_DESC(phyaddr, "Physical device address");
78 #define STMMAC_TX_THRESH(x) ((x)->dma_conf.dma_tx_size / 4)
79 #define STMMAC_RX_THRESH(x) ((x)->dma_conf.dma_rx_size / 4)
81 /* Limit to make sure XDP TX and slow path can coexist */
82 #define STMMAC_XSK_TX_BUDGET_MAX 256
83 #define STMMAC_TX_XSK_AVAIL 16
84 #define STMMAC_RX_FILL_BATCH 16
86 #define STMMAC_XDP_PASS 0
87 #define STMMAC_XDP_CONSUMED BIT(0)
88 #define STMMAC_XDP_TX BIT(1)
89 #define STMMAC_XDP_REDIRECT BIT(2)
91 static int flow_ctrl = FLOW_AUTO;
92 module_param(flow_ctrl, int, 0644);
93 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
95 static int pause = PAUSE_TIME;
96 module_param(pause, int, 0644);
97 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
100 static int tc = TC_DEFAULT;
101 module_param(tc, int, 0644);
102 MODULE_PARM_DESC(tc, "DMA threshold control value");
104 #define DEFAULT_BUFSIZE 1536
105 static int buf_sz = DEFAULT_BUFSIZE;
106 module_param(buf_sz, int, 0644);
107 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
109 #define STMMAC_RX_COPYBREAK 256
111 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
112 NETIF_MSG_LINK | NETIF_MSG_IFUP |
113 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
115 #define STMMAC_DEFAULT_LPI_TIMER 1000
116 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
117 module_param(eee_timer, int, 0644);
118 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
119 #define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x))
121 /* By default the driver will use the ring mode to manage tx and rx descriptors,
122 * but allow user to force to use the chain instead of the ring
124 static unsigned int chain_mode;
125 module_param(chain_mode, int, 0444);
126 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
128 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
129 /* For MSI interrupts handling */
130 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id);
131 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id);
132 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data);
133 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data);
134 static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue);
135 static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue);
136 static void stmmac_reset_queues_param(struct stmmac_priv *priv);
137 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue);
138 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue);
139 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
140 u32 rxmode, u32 chan);
142 #ifdef CONFIG_DEBUG_FS
143 static const struct net_device_ops stmmac_netdev_ops;
144 static void stmmac_init_fs(struct net_device *dev);
145 static void stmmac_exit_fs(struct net_device *dev);
148 #define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC))
150 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled)
155 ret = clk_prepare_enable(priv->plat->stmmac_clk);
158 ret = clk_prepare_enable(priv->plat->pclk);
160 clk_disable_unprepare(priv->plat->stmmac_clk);
163 if (priv->plat->clks_config) {
164 ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled);
166 clk_disable_unprepare(priv->plat->stmmac_clk);
167 clk_disable_unprepare(priv->plat->pclk);
172 clk_disable_unprepare(priv->plat->stmmac_clk);
173 clk_disable_unprepare(priv->plat->pclk);
174 if (priv->plat->clks_config)
175 priv->plat->clks_config(priv->plat->bsp_priv, enabled);
180 EXPORT_SYMBOL_GPL(stmmac_bus_clks_config);
183 * stmmac_verify_args - verify the driver parameters.
184 * Description: it checks the driver parameters and set a default in case of
187 static void stmmac_verify_args(void)
189 if (unlikely(watchdog < 0))
191 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
192 buf_sz = DEFAULT_BUFSIZE;
193 if (unlikely(flow_ctrl > 1))
194 flow_ctrl = FLOW_AUTO;
195 else if (likely(flow_ctrl < 0))
196 flow_ctrl = FLOW_OFF;
197 if (unlikely((pause < 0) || (pause > 0xffff)))
200 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
203 static void __stmmac_disable_all_queues(struct stmmac_priv *priv)
205 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
206 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
207 u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
210 for (queue = 0; queue < maxq; queue++) {
211 struct stmmac_channel *ch = &priv->channel[queue];
213 if (stmmac_xdp_is_enabled(priv) &&
214 test_bit(queue, priv->af_xdp_zc_qps)) {
215 napi_disable(&ch->rxtx_napi);
219 if (queue < rx_queues_cnt)
220 napi_disable(&ch->rx_napi);
221 if (queue < tx_queues_cnt)
222 napi_disable(&ch->tx_napi);
227 * stmmac_disable_all_queues - Disable all queues
228 * @priv: driver private structure
230 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
232 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
233 struct stmmac_rx_queue *rx_q;
236 /* synchronize_rcu() needed for pending XDP buffers to drain */
237 for (queue = 0; queue < rx_queues_cnt; queue++) {
238 rx_q = &priv->dma_conf.rx_queue[queue];
239 if (rx_q->xsk_pool) {
245 __stmmac_disable_all_queues(priv);
249 * stmmac_enable_all_queues - Enable all queues
250 * @priv: driver private structure
252 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
254 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
255 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
256 u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
259 for (queue = 0; queue < maxq; queue++) {
260 struct stmmac_channel *ch = &priv->channel[queue];
262 if (stmmac_xdp_is_enabled(priv) &&
263 test_bit(queue, priv->af_xdp_zc_qps)) {
264 napi_enable(&ch->rxtx_napi);
268 if (queue < rx_queues_cnt)
269 napi_enable(&ch->rx_napi);
270 if (queue < tx_queues_cnt)
271 napi_enable(&ch->tx_napi);
275 static void stmmac_service_event_schedule(struct stmmac_priv *priv)
277 if (!test_bit(STMMAC_DOWN, &priv->state) &&
278 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state))
279 queue_work(priv->wq, &priv->service_task);
282 static void stmmac_global_err(struct stmmac_priv *priv)
284 netif_carrier_off(priv->dev);
285 set_bit(STMMAC_RESET_REQUESTED, &priv->state);
286 stmmac_service_event_schedule(priv);
290 * stmmac_clk_csr_set - dynamically set the MDC clock
291 * @priv: driver private structure
292 * Description: this is to dynamically set the MDC clock according to the csr
295 * If a specific clk_csr value is passed from the platform
296 * this means that the CSR Clock Range selection cannot be
297 * changed at run-time and it is fixed (as reported in the driver
298 * documentation). Viceversa the driver will try to set the MDC
299 * clock dynamically according to the actual clock input.
301 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
305 clk_rate = clk_get_rate(priv->plat->stmmac_clk);
307 /* Platform provided default clk_csr would be assumed valid
308 * for all other cases except for the below mentioned ones.
309 * For values higher than the IEEE 802.3 specified frequency
310 * we can not estimate the proper divider as it is not known
311 * the frequency of clk_csr_i. So we do not change the default
314 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
315 if (clk_rate < CSR_F_35M)
316 priv->clk_csr = STMMAC_CSR_20_35M;
317 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
318 priv->clk_csr = STMMAC_CSR_35_60M;
319 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
320 priv->clk_csr = STMMAC_CSR_60_100M;
321 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
322 priv->clk_csr = STMMAC_CSR_100_150M;
323 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
324 priv->clk_csr = STMMAC_CSR_150_250M;
325 else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M))
326 priv->clk_csr = STMMAC_CSR_250_300M;
329 if (priv->plat->flags & STMMAC_FLAG_HAS_SUN8I) {
330 if (clk_rate > 160000000)
331 priv->clk_csr = 0x03;
332 else if (clk_rate > 80000000)
333 priv->clk_csr = 0x02;
334 else if (clk_rate > 40000000)
335 priv->clk_csr = 0x01;
340 if (priv->plat->has_xgmac) {
341 if (clk_rate > 400000000)
343 else if (clk_rate > 350000000)
345 else if (clk_rate > 300000000)
347 else if (clk_rate > 250000000)
349 else if (clk_rate > 150000000)
356 static void print_pkt(unsigned char *buf, int len)
358 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
359 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
362 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
364 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
367 if (tx_q->dirty_tx > tx_q->cur_tx)
368 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
370 avail = priv->dma_conf.dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1;
376 * stmmac_rx_dirty - Get RX queue dirty
377 * @priv: driver private structure
378 * @queue: RX queue index
380 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
382 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
385 if (rx_q->dirty_rx <= rx_q->cur_rx)
386 dirty = rx_q->cur_rx - rx_q->dirty_rx;
388 dirty = priv->dma_conf.dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx;
393 static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en)
397 /* Clear/set the SW EEE timer flag based on LPI ET enablement */
398 priv->eee_sw_timer_en = en ? 0 : 1;
399 tx_lpi_timer = en ? priv->tx_lpi_timer : 0;
400 stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer);
404 * stmmac_enable_eee_mode - check and enter in LPI mode
405 * @priv: driver private structure
406 * Description: this function is to verify and enter in LPI mode in case of
409 static int stmmac_enable_eee_mode(struct stmmac_priv *priv)
411 u32 tx_cnt = priv->plat->tx_queues_to_use;
414 /* check if all TX queues have the work finished */
415 for (queue = 0; queue < tx_cnt; queue++) {
416 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
418 if (tx_q->dirty_tx != tx_q->cur_tx)
419 return -EBUSY; /* still unfinished work */
422 /* Check and enter in LPI mode */
423 if (!priv->tx_path_in_lpi_mode)
424 stmmac_set_eee_mode(priv, priv->hw,
425 priv->plat->flags & STMMAC_FLAG_EN_TX_LPI_CLOCKGATING);
430 * stmmac_disable_eee_mode - disable and exit from LPI mode
431 * @priv: driver private structure
432 * Description: this function is to exit and disable EEE in case of
433 * LPI state is true. This is called by the xmit.
435 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
437 if (!priv->eee_sw_timer_en) {
438 stmmac_lpi_entry_timer_config(priv, 0);
442 stmmac_reset_eee_mode(priv, priv->hw);
443 del_timer_sync(&priv->eee_ctrl_timer);
444 priv->tx_path_in_lpi_mode = false;
448 * stmmac_eee_ctrl_timer - EEE TX SW timer.
449 * @t: timer_list struct containing private info
451 * if there is no data transfer and if we are not in LPI state,
452 * then MAC Transmitter can be moved to LPI state.
454 static void stmmac_eee_ctrl_timer(struct timer_list *t)
456 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer);
458 if (stmmac_enable_eee_mode(priv))
459 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer));
463 * stmmac_eee_init - init EEE
464 * @priv: driver private structure
466 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
467 * can also manage EEE, this function enable the LPI state and start related
470 bool stmmac_eee_init(struct stmmac_priv *priv)
472 int eee_tw_timer = priv->eee_tw_timer;
474 /* Using PCS we cannot dial with the phy registers at this stage
475 * so we do not support extra feature like EEE.
477 if (priv->hw->pcs == STMMAC_PCS_TBI ||
478 priv->hw->pcs == STMMAC_PCS_RTBI)
481 /* Check if MAC core supports the EEE feature. */
482 if (!priv->dma_cap.eee)
485 mutex_lock(&priv->lock);
487 /* Check if it needs to be deactivated */
488 if (!priv->eee_active) {
489 if (priv->eee_enabled) {
490 netdev_dbg(priv->dev, "disable EEE\n");
491 stmmac_lpi_entry_timer_config(priv, 0);
492 del_timer_sync(&priv->eee_ctrl_timer);
493 stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer);
495 xpcs_config_eee(priv->hw->xpcs,
496 priv->plat->mult_fact_100ns,
499 mutex_unlock(&priv->lock);
503 if (priv->eee_active && !priv->eee_enabled) {
504 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0);
505 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS,
508 xpcs_config_eee(priv->hw->xpcs,
509 priv->plat->mult_fact_100ns,
513 if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) {
514 del_timer_sync(&priv->eee_ctrl_timer);
515 priv->tx_path_in_lpi_mode = false;
516 stmmac_lpi_entry_timer_config(priv, 1);
518 stmmac_lpi_entry_timer_config(priv, 0);
519 mod_timer(&priv->eee_ctrl_timer,
520 STMMAC_LPI_T(priv->tx_lpi_timer));
523 mutex_unlock(&priv->lock);
524 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
528 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
529 * @priv: driver private structure
530 * @p : descriptor pointer
531 * @skb : the socket buffer
533 * This function will read timestamp from the descriptor & pass it to stack.
534 * and also perform some sanity checks.
536 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
537 struct dma_desc *p, struct sk_buff *skb)
539 struct skb_shared_hwtstamps shhwtstamp;
543 if (!priv->hwts_tx_en)
546 /* exit if skb doesn't support hw tstamp */
547 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
550 /* check tx tstamp status */
551 if (stmmac_get_tx_timestamp_status(priv, p)) {
552 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
554 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) {
559 ns -= priv->plat->cdc_error_adj;
561 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
562 shhwtstamp.hwtstamp = ns_to_ktime(ns);
564 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
565 /* pass tstamp to stack */
566 skb_tstamp_tx(skb, &shhwtstamp);
570 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
571 * @priv: driver private structure
572 * @p : descriptor pointer
573 * @np : next descriptor pointer
574 * @skb : the socket buffer
576 * This function will read received packet's timestamp from the descriptor
577 * and pass it to stack. It also perform some sanity checks.
579 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
580 struct dma_desc *np, struct sk_buff *skb)
582 struct skb_shared_hwtstamps *shhwtstamp = NULL;
583 struct dma_desc *desc = p;
586 if (!priv->hwts_rx_en)
588 /* For GMAC4, the valid timestamp is from CTX next desc. */
589 if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
592 /* Check if timestamp is available */
593 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
594 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
596 ns -= priv->plat->cdc_error_adj;
598 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
599 shhwtstamp = skb_hwtstamps(skb);
600 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
601 shhwtstamp->hwtstamp = ns_to_ktime(ns);
603 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
608 * stmmac_hwtstamp_set - control hardware timestamping.
609 * @dev: device pointer.
610 * @ifr: An IOCTL specific structure, that can contain a pointer to
611 * a proprietary structure used to pass information to the driver.
613 * This function configures the MAC to enable/disable both outgoing(TX)
614 * and incoming(RX) packets time stamping based on user input.
616 * 0 on success and an appropriate -ve integer on failure.
618 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
620 struct stmmac_priv *priv = netdev_priv(dev);
621 struct hwtstamp_config config;
624 u32 ptp_over_ipv4_udp = 0;
625 u32 ptp_over_ipv6_udp = 0;
626 u32 ptp_over_ethernet = 0;
627 u32 snap_type_sel = 0;
628 u32 ts_master_en = 0;
631 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
632 netdev_alert(priv->dev, "No support for HW time stamping\n");
633 priv->hwts_tx_en = 0;
634 priv->hwts_rx_en = 0;
639 if (copy_from_user(&config, ifr->ifr_data,
643 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
644 __func__, config.flags, config.tx_type, config.rx_filter);
646 if (config.tx_type != HWTSTAMP_TX_OFF &&
647 config.tx_type != HWTSTAMP_TX_ON)
651 switch (config.rx_filter) {
652 case HWTSTAMP_FILTER_NONE:
653 /* time stamp no incoming packet at all */
654 config.rx_filter = HWTSTAMP_FILTER_NONE;
657 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
658 /* PTP v1, UDP, any kind of event packet */
659 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
660 /* 'xmac' hardware can support Sync, Pdelay_Req and
661 * Pdelay_resp by setting bit14 and bits17/16 to 01
662 * This leaves Delay_Req timestamps out.
663 * Enable all events *and* general purpose message
666 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
667 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
668 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
671 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
672 /* PTP v1, UDP, Sync packet */
673 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
674 /* take time stamp for SYNC messages only */
675 ts_event_en = PTP_TCR_TSEVNTENA;
677 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
678 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
681 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
682 /* PTP v1, UDP, Delay_req packet */
683 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
684 /* take time stamp for Delay_Req messages only */
685 ts_master_en = PTP_TCR_TSMSTRENA;
686 ts_event_en = PTP_TCR_TSEVNTENA;
688 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
689 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
692 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
693 /* PTP v2, UDP, any kind of event packet */
694 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
695 ptp_v2 = PTP_TCR_TSVER2ENA;
696 /* take time stamp for all event messages */
697 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
699 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
700 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
703 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
704 /* PTP v2, UDP, Sync packet */
705 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
706 ptp_v2 = PTP_TCR_TSVER2ENA;
707 /* take time stamp for SYNC messages only */
708 ts_event_en = PTP_TCR_TSEVNTENA;
710 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
711 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
714 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
715 /* PTP v2, UDP, Delay_req packet */
716 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
717 ptp_v2 = PTP_TCR_TSVER2ENA;
718 /* take time stamp for Delay_Req messages only */
719 ts_master_en = PTP_TCR_TSMSTRENA;
720 ts_event_en = PTP_TCR_TSEVNTENA;
722 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
723 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
726 case HWTSTAMP_FILTER_PTP_V2_EVENT:
727 /* PTP v2/802.AS1 any layer, any kind of event packet */
728 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
729 ptp_v2 = PTP_TCR_TSVER2ENA;
730 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
731 if (priv->synopsys_id < DWMAC_CORE_4_10)
732 ts_event_en = PTP_TCR_TSEVNTENA;
733 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
734 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
735 ptp_over_ethernet = PTP_TCR_TSIPENA;
738 case HWTSTAMP_FILTER_PTP_V2_SYNC:
739 /* PTP v2/802.AS1, any layer, Sync packet */
740 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
741 ptp_v2 = PTP_TCR_TSVER2ENA;
742 /* take time stamp for SYNC messages only */
743 ts_event_en = PTP_TCR_TSEVNTENA;
745 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
746 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
747 ptp_over_ethernet = PTP_TCR_TSIPENA;
750 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
751 /* PTP v2/802.AS1, any layer, Delay_req packet */
752 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
753 ptp_v2 = PTP_TCR_TSVER2ENA;
754 /* take time stamp for Delay_Req messages only */
755 ts_master_en = PTP_TCR_TSMSTRENA;
756 ts_event_en = PTP_TCR_TSEVNTENA;
758 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
759 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
760 ptp_over_ethernet = PTP_TCR_TSIPENA;
763 case HWTSTAMP_FILTER_NTP_ALL:
764 case HWTSTAMP_FILTER_ALL:
765 /* time stamp any incoming packet */
766 config.rx_filter = HWTSTAMP_FILTER_ALL;
767 tstamp_all = PTP_TCR_TSENALL;
774 switch (config.rx_filter) {
775 case HWTSTAMP_FILTER_NONE:
776 config.rx_filter = HWTSTAMP_FILTER_NONE;
779 /* PTP v1, UDP, any kind of event packet */
780 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
784 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
785 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
787 priv->systime_flags = STMMAC_HWTS_ACTIVE;
789 if (priv->hwts_tx_en || priv->hwts_rx_en) {
790 priv->systime_flags |= tstamp_all | ptp_v2 |
791 ptp_over_ethernet | ptp_over_ipv6_udp |
792 ptp_over_ipv4_udp | ts_event_en |
793 ts_master_en | snap_type_sel;
796 stmmac_config_hw_tstamping(priv, priv->ptpaddr, priv->systime_flags);
798 memcpy(&priv->tstamp_config, &config, sizeof(config));
800 return copy_to_user(ifr->ifr_data, &config,
801 sizeof(config)) ? -EFAULT : 0;
805 * stmmac_hwtstamp_get - read hardware timestamping.
806 * @dev: device pointer.
807 * @ifr: An IOCTL specific structure, that can contain a pointer to
808 * a proprietary structure used to pass information to the driver.
810 * This function obtain the current hardware timestamping settings
813 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
815 struct stmmac_priv *priv = netdev_priv(dev);
816 struct hwtstamp_config *config = &priv->tstamp_config;
818 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
821 return copy_to_user(ifr->ifr_data, config,
822 sizeof(*config)) ? -EFAULT : 0;
826 * stmmac_init_tstamp_counter - init hardware timestamping counter
827 * @priv: driver private structure
828 * @systime_flags: timestamping flags
830 * Initialize hardware counter for packet timestamping.
831 * This is valid as long as the interface is open and not suspended.
832 * Will be rerun after resuming from suspend, case in which the timestamping
833 * flags updated by stmmac_hwtstamp_set() also need to be restored.
835 int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags)
837 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
838 struct timespec64 now;
842 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
845 stmmac_config_hw_tstamping(priv, priv->ptpaddr, systime_flags);
846 priv->systime_flags = systime_flags;
848 /* program Sub Second Increment reg */
849 stmmac_config_sub_second_increment(priv, priv->ptpaddr,
850 priv->plat->clk_ptp_rate,
852 temp = div_u64(1000000000ULL, sec_inc);
854 /* Store sub second increment for later use */
855 priv->sub_second_inc = sec_inc;
857 /* calculate default added value:
859 * addend = (2^32)/freq_div_ratio;
860 * where, freq_div_ratio = 1e9ns/sec_inc
862 temp = (u64)(temp << 32);
863 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
864 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);
866 /* initialize system time */
867 ktime_get_real_ts64(&now);
869 /* lower 32 bits of tv_sec are safe until y2106 */
870 stmmac_init_systime(priv, priv->ptpaddr, (u32)now.tv_sec, now.tv_nsec);
874 EXPORT_SYMBOL_GPL(stmmac_init_tstamp_counter);
877 * stmmac_init_ptp - init PTP
878 * @priv: driver private structure
879 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
880 * This is done by looking at the HW cap. register.
881 * This function also registers the ptp driver.
883 static int stmmac_init_ptp(struct stmmac_priv *priv)
885 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
888 if (priv->plat->ptp_clk_freq_config)
889 priv->plat->ptp_clk_freq_config(priv);
891 ret = stmmac_init_tstamp_counter(priv, STMMAC_HWTS_ACTIVE);
896 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */
897 if (xmac && priv->dma_cap.atime_stamp)
899 /* Dwmac 3.x core with extend_desc can support adv_ts */
900 else if (priv->extend_desc && priv->dma_cap.atime_stamp)
903 if (priv->dma_cap.time_stamp)
904 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
907 netdev_info(priv->dev,
908 "IEEE 1588-2008 Advanced Timestamp supported\n");
910 priv->hwts_tx_en = 0;
911 priv->hwts_rx_en = 0;
913 if (priv->plat->flags & STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY)
914 stmmac_hwtstamp_correct_latency(priv, priv);
919 static void stmmac_release_ptp(struct stmmac_priv *priv)
921 clk_disable_unprepare(priv->plat->clk_ptp_ref);
922 stmmac_ptp_unregister(priv);
926 * stmmac_mac_flow_ctrl - Configure flow control in all queues
927 * @priv: driver private structure
928 * @duplex: duplex passed to the next function
929 * Description: It is used for configuring the flow control in all queues
931 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
933 u32 tx_cnt = priv->plat->tx_queues_to_use;
935 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
936 priv->pause, tx_cnt);
939 static struct phylink_pcs *stmmac_mac_select_pcs(struct phylink_config *config,
940 phy_interface_t interface)
942 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
945 return &priv->hw->xpcs->pcs;
947 if (priv->hw->lynx_pcs)
948 return priv->hw->lynx_pcs;
953 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode,
954 const struct phylink_link_state *state)
956 /* Nothing to do, xpcs_config() handles everything */
959 static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up)
961 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
962 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
963 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
964 bool *hs_enable = &fpe_cfg->hs_enable;
966 if (is_up && *hs_enable) {
967 stmmac_fpe_send_mpacket(priv, priv->ioaddr, fpe_cfg,
970 *lo_state = FPE_STATE_OFF;
971 *lp_state = FPE_STATE_OFF;
975 static void stmmac_mac_link_down(struct phylink_config *config,
976 unsigned int mode, phy_interface_t interface)
978 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
980 stmmac_mac_set(priv, priv->ioaddr, false);
981 priv->eee_active = false;
982 priv->tx_lpi_enabled = false;
983 priv->eee_enabled = stmmac_eee_init(priv);
984 stmmac_set_eee_pls(priv, priv->hw, false);
986 if (priv->dma_cap.fpesel)
987 stmmac_fpe_link_state_handle(priv, false);
990 static void stmmac_mac_link_up(struct phylink_config *config,
991 struct phy_device *phy,
992 unsigned int mode, phy_interface_t interface,
993 int speed, int duplex,
994 bool tx_pause, bool rx_pause)
996 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
999 if ((priv->plat->flags & STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP) &&
1000 priv->plat->serdes_powerup)
1001 priv->plat->serdes_powerup(priv->dev, priv->plat->bsp_priv);
1003 old_ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
1004 ctrl = old_ctrl & ~priv->hw->link.speed_mask;
1006 if (interface == PHY_INTERFACE_MODE_USXGMII) {
1009 ctrl |= priv->hw->link.xgmii.speed10000;
1012 ctrl |= priv->hw->link.xgmii.speed5000;
1015 ctrl |= priv->hw->link.xgmii.speed2500;
1020 } else if (interface == PHY_INTERFACE_MODE_XLGMII) {
1023 ctrl |= priv->hw->link.xlgmii.speed100000;
1026 ctrl |= priv->hw->link.xlgmii.speed50000;
1029 ctrl |= priv->hw->link.xlgmii.speed40000;
1032 ctrl |= priv->hw->link.xlgmii.speed25000;
1035 ctrl |= priv->hw->link.xgmii.speed10000;
1038 ctrl |= priv->hw->link.speed2500;
1041 ctrl |= priv->hw->link.speed1000;
1049 ctrl |= priv->hw->link.speed2500;
1052 ctrl |= priv->hw->link.speed1000;
1055 ctrl |= priv->hw->link.speed100;
1058 ctrl |= priv->hw->link.speed10;
1065 priv->speed = speed;
1067 if (priv->plat->fix_mac_speed)
1068 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed, mode);
1071 ctrl &= ~priv->hw->link.duplex;
1073 ctrl |= priv->hw->link.duplex;
1075 /* Flow Control operation */
1076 if (rx_pause && tx_pause)
1077 priv->flow_ctrl = FLOW_AUTO;
1078 else if (rx_pause && !tx_pause)
1079 priv->flow_ctrl = FLOW_RX;
1080 else if (!rx_pause && tx_pause)
1081 priv->flow_ctrl = FLOW_TX;
1083 priv->flow_ctrl = FLOW_OFF;
1085 stmmac_mac_flow_ctrl(priv, duplex);
1087 if (ctrl != old_ctrl)
1088 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
1090 stmmac_mac_set(priv, priv->ioaddr, true);
1091 if (phy && priv->dma_cap.eee) {
1093 phy_init_eee(phy, !(priv->plat->flags &
1094 STMMAC_FLAG_RX_CLK_RUNS_IN_LPI)) >= 0;
1095 priv->eee_enabled = stmmac_eee_init(priv);
1096 priv->tx_lpi_enabled = priv->eee_enabled;
1097 stmmac_set_eee_pls(priv, priv->hw, true);
1100 if (priv->dma_cap.fpesel)
1101 stmmac_fpe_link_state_handle(priv, true);
1103 if (priv->plat->flags & STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY)
1104 stmmac_hwtstamp_correct_latency(priv, priv);
1107 static const struct phylink_mac_ops stmmac_phylink_mac_ops = {
1108 .mac_select_pcs = stmmac_mac_select_pcs,
1109 .mac_config = stmmac_mac_config,
1110 .mac_link_down = stmmac_mac_link_down,
1111 .mac_link_up = stmmac_mac_link_up,
1115 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
1116 * @priv: driver private structure
1117 * Description: this is to verify if the HW supports the PCS.
1118 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
1119 * configured for the TBI, RTBI, or SGMII PHY interface.
1121 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
1123 int interface = priv->plat->mac_interface;
1125 if (priv->dma_cap.pcs) {
1126 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
1127 (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1128 (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1129 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
1130 netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
1131 priv->hw->pcs = STMMAC_PCS_RGMII;
1132 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
1133 netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
1134 priv->hw->pcs = STMMAC_PCS_SGMII;
1140 * stmmac_init_phy - PHY initialization
1141 * @dev: net device structure
1142 * Description: it initializes the driver's PHY state, and attaches the PHY
1143 * to the mac driver.
1147 static int stmmac_init_phy(struct net_device *dev)
1149 struct stmmac_priv *priv = netdev_priv(dev);
1150 struct fwnode_handle *phy_fwnode;
1151 struct fwnode_handle *fwnode;
1154 if (!phylink_expects_phy(priv->phylink))
1157 fwnode = priv->plat->port_node;
1159 fwnode = dev_fwnode(priv->device);
1162 phy_fwnode = fwnode_get_phy_node(fwnode);
1166 /* Some DT bindings do not set-up the PHY handle. Let's try to
1169 if (!phy_fwnode || IS_ERR(phy_fwnode)) {
1170 int addr = priv->plat->phy_addr;
1171 struct phy_device *phydev;
1174 netdev_err(priv->dev, "no phy found\n");
1178 phydev = mdiobus_get_phy(priv->mii, addr);
1180 netdev_err(priv->dev, "no phy at addr %d\n", addr);
1184 ret = phylink_connect_phy(priv->phylink, phydev);
1186 fwnode_handle_put(phy_fwnode);
1187 ret = phylink_fwnode_phy_connect(priv->phylink, fwnode, 0);
1190 if (!priv->plat->pmt) {
1191 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };
1193 phylink_ethtool_get_wol(priv->phylink, &wol);
1194 device_set_wakeup_capable(priv->device, !!wol.supported);
1195 device_set_wakeup_enable(priv->device, !!wol.wolopts);
1201 static void stmmac_set_half_duplex(struct stmmac_priv *priv)
1203 /* Half-Duplex can only work with single tx queue */
1204 if (priv->plat->tx_queues_to_use > 1)
1205 priv->phylink_config.mac_capabilities &=
1206 ~(MAC_10HD | MAC_100HD | MAC_1000HD);
1208 priv->phylink_config.mac_capabilities |=
1209 (MAC_10HD | MAC_100HD | MAC_1000HD);
1212 static int stmmac_phy_setup(struct stmmac_priv *priv)
1214 struct stmmac_mdio_bus_data *mdio_bus_data;
1215 int mode = priv->plat->phy_interface;
1216 struct fwnode_handle *fwnode;
1217 struct phylink *phylink;
1220 priv->phylink_config.dev = &priv->dev->dev;
1221 priv->phylink_config.type = PHYLINK_NETDEV;
1222 priv->phylink_config.mac_managed_pm = true;
1224 mdio_bus_data = priv->plat->mdio_bus_data;
1226 priv->phylink_config.ovr_an_inband =
1227 mdio_bus_data->xpcs_an_inband;
1229 /* Set the platform/firmware specified interface mode. Note, phylink
1230 * deals with the PHY interface mode, not the MAC interface mode.
1232 __set_bit(mode, priv->phylink_config.supported_interfaces);
1234 /* If we have an xpcs, it defines which PHY interfaces are supported. */
1236 xpcs_get_interfaces(priv->hw->xpcs,
1237 priv->phylink_config.supported_interfaces);
1239 priv->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1240 MAC_10FD | MAC_100FD |
1243 stmmac_set_half_duplex(priv);
1245 /* Get the MAC specific capabilities */
1246 stmmac_mac_phylink_get_caps(priv);
1248 max_speed = priv->plat->max_speed;
1250 phylink_limit_mac_speed(&priv->phylink_config, max_speed);
1252 fwnode = priv->plat->port_node;
1254 fwnode = dev_fwnode(priv->device);
1256 phylink = phylink_create(&priv->phylink_config, fwnode,
1257 mode, &stmmac_phylink_mac_ops);
1258 if (IS_ERR(phylink))
1259 return PTR_ERR(phylink);
1261 priv->phylink = phylink;
1265 static void stmmac_display_rx_rings(struct stmmac_priv *priv,
1266 struct stmmac_dma_conf *dma_conf)
1268 u32 rx_cnt = priv->plat->rx_queues_to_use;
1269 unsigned int desc_size;
1273 /* Display RX rings */
1274 for (queue = 0; queue < rx_cnt; queue++) {
1275 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1277 pr_info("\tRX Queue %u rings\n", queue);
1279 if (priv->extend_desc) {
1280 head_rx = (void *)rx_q->dma_erx;
1281 desc_size = sizeof(struct dma_extended_desc);
1283 head_rx = (void *)rx_q->dma_rx;
1284 desc_size = sizeof(struct dma_desc);
1287 /* Display RX ring */
1288 stmmac_display_ring(priv, head_rx, dma_conf->dma_rx_size, true,
1289 rx_q->dma_rx_phy, desc_size);
1293 static void stmmac_display_tx_rings(struct stmmac_priv *priv,
1294 struct stmmac_dma_conf *dma_conf)
1296 u32 tx_cnt = priv->plat->tx_queues_to_use;
1297 unsigned int desc_size;
1301 /* Display TX rings */
1302 for (queue = 0; queue < tx_cnt; queue++) {
1303 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue];
1305 pr_info("\tTX Queue %d rings\n", queue);
1307 if (priv->extend_desc) {
1308 head_tx = (void *)tx_q->dma_etx;
1309 desc_size = sizeof(struct dma_extended_desc);
1310 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) {
1311 head_tx = (void *)tx_q->dma_entx;
1312 desc_size = sizeof(struct dma_edesc);
1314 head_tx = (void *)tx_q->dma_tx;
1315 desc_size = sizeof(struct dma_desc);
1318 stmmac_display_ring(priv, head_tx, dma_conf->dma_tx_size, false,
1319 tx_q->dma_tx_phy, desc_size);
1323 static void stmmac_display_rings(struct stmmac_priv *priv,
1324 struct stmmac_dma_conf *dma_conf)
1326 /* Display RX ring */
1327 stmmac_display_rx_rings(priv, dma_conf);
1329 /* Display TX ring */
1330 stmmac_display_tx_rings(priv, dma_conf);
1333 static int stmmac_set_bfsize(int mtu, int bufsize)
1337 if (mtu >= BUF_SIZE_8KiB)
1338 ret = BUF_SIZE_16KiB;
1339 else if (mtu >= BUF_SIZE_4KiB)
1340 ret = BUF_SIZE_8KiB;
1341 else if (mtu >= BUF_SIZE_2KiB)
1342 ret = BUF_SIZE_4KiB;
1343 else if (mtu > DEFAULT_BUFSIZE)
1344 ret = BUF_SIZE_2KiB;
1346 ret = DEFAULT_BUFSIZE;
1352 * stmmac_clear_rx_descriptors - clear RX descriptors
1353 * @priv: driver private structure
1354 * @dma_conf: structure to take the dma data
1355 * @queue: RX queue index
1356 * Description: this function is called to clear the RX descriptors
1357 * in case of both basic and extended descriptors are used.
1359 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv,
1360 struct stmmac_dma_conf *dma_conf,
1363 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1366 /* Clear the RX descriptors */
1367 for (i = 0; i < dma_conf->dma_rx_size; i++)
1368 if (priv->extend_desc)
1369 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
1370 priv->use_riwt, priv->mode,
1371 (i == dma_conf->dma_rx_size - 1),
1372 dma_conf->dma_buf_sz);
1374 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
1375 priv->use_riwt, priv->mode,
1376 (i == dma_conf->dma_rx_size - 1),
1377 dma_conf->dma_buf_sz);
1381 * stmmac_clear_tx_descriptors - clear tx descriptors
1382 * @priv: driver private structure
1383 * @dma_conf: structure to take the dma data
1384 * @queue: TX queue index.
1385 * Description: this function is called to clear the TX descriptors
1386 * in case of both basic and extended descriptors are used.
1388 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv,
1389 struct stmmac_dma_conf *dma_conf,
1392 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue];
1395 /* Clear the TX descriptors */
1396 for (i = 0; i < dma_conf->dma_tx_size; i++) {
1397 int last = (i == (dma_conf->dma_tx_size - 1));
1400 if (priv->extend_desc)
1401 p = &tx_q->dma_etx[i].basic;
1402 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
1403 p = &tx_q->dma_entx[i].basic;
1405 p = &tx_q->dma_tx[i];
1407 stmmac_init_tx_desc(priv, p, priv->mode, last);
1412 * stmmac_clear_descriptors - clear descriptors
1413 * @priv: driver private structure
1414 * @dma_conf: structure to take the dma data
1415 * Description: this function is called to clear the TX and RX descriptors
1416 * in case of both basic and extended descriptors are used.
1418 static void stmmac_clear_descriptors(struct stmmac_priv *priv,
1419 struct stmmac_dma_conf *dma_conf)
1421 u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1422 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1425 /* Clear the RX descriptors */
1426 for (queue = 0; queue < rx_queue_cnt; queue++)
1427 stmmac_clear_rx_descriptors(priv, dma_conf, queue);
1429 /* Clear the TX descriptors */
1430 for (queue = 0; queue < tx_queue_cnt; queue++)
1431 stmmac_clear_tx_descriptors(priv, dma_conf, queue);
1435 * stmmac_init_rx_buffers - init the RX descriptor buffer.
1436 * @priv: driver private structure
1437 * @dma_conf: structure to take the dma data
1438 * @p: descriptor pointer
1439 * @i: descriptor index
1441 * @queue: RX queue index
1442 * Description: this function is called to allocate a receive buffer, perform
1443 * the DMA mapping and init the descriptor.
1445 static int stmmac_init_rx_buffers(struct stmmac_priv *priv,
1446 struct stmmac_dma_conf *dma_conf,
1448 int i, gfp_t flags, u32 queue)
1450 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1451 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1452 gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN);
1454 if (priv->dma_cap.host_dma_width <= 32)
1458 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp);
1461 buf->page_offset = stmmac_rx_offset(priv);
1464 if (priv->sph && !buf->sec_page) {
1465 buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp);
1469 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
1470 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true);
1472 buf->sec_page = NULL;
1473 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false);
1476 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset;
1478 stmmac_set_desc_addr(priv, p, buf->addr);
1479 if (dma_conf->dma_buf_sz == BUF_SIZE_16KiB)
1480 stmmac_init_desc3(priv, p);
1486 * stmmac_free_rx_buffer - free RX dma buffers
1487 * @priv: private structure
1491 static void stmmac_free_rx_buffer(struct stmmac_priv *priv,
1492 struct stmmac_rx_queue *rx_q,
1495 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1498 page_pool_put_full_page(rx_q->page_pool, buf->page, false);
1502 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false);
1503 buf->sec_page = NULL;
1507 * stmmac_free_tx_buffer - free RX dma buffers
1508 * @priv: private structure
1509 * @dma_conf: structure to take the dma data
1510 * @queue: RX queue index
1513 static void stmmac_free_tx_buffer(struct stmmac_priv *priv,
1514 struct stmmac_dma_conf *dma_conf,
1517 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue];
1519 if (tx_q->tx_skbuff_dma[i].buf &&
1520 tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) {
1521 if (tx_q->tx_skbuff_dma[i].map_as_page)
1522 dma_unmap_page(priv->device,
1523 tx_q->tx_skbuff_dma[i].buf,
1524 tx_q->tx_skbuff_dma[i].len,
1527 dma_unmap_single(priv->device,
1528 tx_q->tx_skbuff_dma[i].buf,
1529 tx_q->tx_skbuff_dma[i].len,
1533 if (tx_q->xdpf[i] &&
1534 (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_TX ||
1535 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_NDO)) {
1536 xdp_return_frame(tx_q->xdpf[i]);
1537 tx_q->xdpf[i] = NULL;
1540 if (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XSK_TX)
1541 tx_q->xsk_frames_done++;
1543 if (tx_q->tx_skbuff[i] &&
1544 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_SKB) {
1545 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1546 tx_q->tx_skbuff[i] = NULL;
1549 tx_q->tx_skbuff_dma[i].buf = 0;
1550 tx_q->tx_skbuff_dma[i].map_as_page = false;
1554 * dma_free_rx_skbufs - free RX dma buffers
1555 * @priv: private structure
1556 * @dma_conf: structure to take the dma data
1557 * @queue: RX queue index
1559 static void dma_free_rx_skbufs(struct stmmac_priv *priv,
1560 struct stmmac_dma_conf *dma_conf,
1563 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1566 for (i = 0; i < dma_conf->dma_rx_size; i++)
1567 stmmac_free_rx_buffer(priv, rx_q, i);
1570 static int stmmac_alloc_rx_buffers(struct stmmac_priv *priv,
1571 struct stmmac_dma_conf *dma_conf,
1572 u32 queue, gfp_t flags)
1574 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1577 for (i = 0; i < dma_conf->dma_rx_size; i++) {
1581 if (priv->extend_desc)
1582 p = &((rx_q->dma_erx + i)->basic);
1584 p = rx_q->dma_rx + i;
1586 ret = stmmac_init_rx_buffers(priv, dma_conf, p, i, flags,
1591 rx_q->buf_alloc_num++;
1598 * dma_free_rx_xskbufs - free RX dma buffers from XSK pool
1599 * @priv: private structure
1600 * @dma_conf: structure to take the dma data
1601 * @queue: RX queue index
1603 static void dma_free_rx_xskbufs(struct stmmac_priv *priv,
1604 struct stmmac_dma_conf *dma_conf,
1607 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1610 for (i = 0; i < dma_conf->dma_rx_size; i++) {
1611 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1616 xsk_buff_free(buf->xdp);
1621 static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv,
1622 struct stmmac_dma_conf *dma_conf,
1625 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1628 /* struct stmmac_xdp_buff is using cb field (maximum size of 24 bytes)
1629 * in struct xdp_buff_xsk to stash driver specific information. Thus,
1630 * use this macro to make sure no size violations.
1632 XSK_CHECK_PRIV_TYPE(struct stmmac_xdp_buff);
1634 for (i = 0; i < dma_conf->dma_rx_size; i++) {
1635 struct stmmac_rx_buffer *buf;
1636 dma_addr_t dma_addr;
1639 if (priv->extend_desc)
1640 p = (struct dma_desc *)(rx_q->dma_erx + i);
1642 p = rx_q->dma_rx + i;
1644 buf = &rx_q->buf_pool[i];
1646 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool);
1650 dma_addr = xsk_buff_xdp_get_dma(buf->xdp);
1651 stmmac_set_desc_addr(priv, p, dma_addr);
1652 rx_q->buf_alloc_num++;
1658 static struct xsk_buff_pool *stmmac_get_xsk_pool(struct stmmac_priv *priv, u32 queue)
1660 if (!stmmac_xdp_is_enabled(priv) || !test_bit(queue, priv->af_xdp_zc_qps))
1663 return xsk_get_pool_from_qid(priv->dev, queue);
1667 * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue)
1668 * @priv: driver private structure
1669 * @dma_conf: structure to take the dma data
1670 * @queue: RX queue index
1672 * Description: this function initializes the DMA RX descriptors
1673 * and allocates the socket buffers. It supports the chained and ring
1676 static int __init_dma_rx_desc_rings(struct stmmac_priv *priv,
1677 struct stmmac_dma_conf *dma_conf,
1678 u32 queue, gfp_t flags)
1680 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1683 netif_dbg(priv, probe, priv->dev,
1684 "(%s) dma_rx_phy=0x%08x\n", __func__,
1685 (u32)rx_q->dma_rx_phy);
1687 stmmac_clear_rx_descriptors(priv, dma_conf, queue);
1689 xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq);
1691 rx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue);
1693 if (rx_q->xsk_pool) {
1694 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq,
1695 MEM_TYPE_XSK_BUFF_POOL,
1697 netdev_info(priv->dev,
1698 "Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n",
1700 xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq);
1702 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq,
1705 netdev_info(priv->dev,
1706 "Register MEM_TYPE_PAGE_POOL RxQ-%d\n",
1710 if (rx_q->xsk_pool) {
1711 /* RX XDP ZC buffer pool may not be populated, e.g.
1714 stmmac_alloc_rx_buffers_zc(priv, dma_conf, queue);
1716 ret = stmmac_alloc_rx_buffers(priv, dma_conf, queue, flags);
1721 /* Setup the chained descriptor addresses */
1722 if (priv->mode == STMMAC_CHAIN_MODE) {
1723 if (priv->extend_desc)
1724 stmmac_mode_init(priv, rx_q->dma_erx,
1726 dma_conf->dma_rx_size, 1);
1728 stmmac_mode_init(priv, rx_q->dma_rx,
1730 dma_conf->dma_rx_size, 0);
1736 static int init_dma_rx_desc_rings(struct net_device *dev,
1737 struct stmmac_dma_conf *dma_conf,
1740 struct stmmac_priv *priv = netdev_priv(dev);
1741 u32 rx_count = priv->plat->rx_queues_to_use;
1745 /* RX INITIALIZATION */
1746 netif_dbg(priv, probe, priv->dev,
1747 "SKB addresses:\nskb\t\tskb data\tdma data\n");
1749 for (queue = 0; queue < rx_count; queue++) {
1750 ret = __init_dma_rx_desc_rings(priv, dma_conf, queue, flags);
1752 goto err_init_rx_buffers;
1757 err_init_rx_buffers:
1758 while (queue >= 0) {
1759 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1762 dma_free_rx_xskbufs(priv, dma_conf, queue);
1764 dma_free_rx_skbufs(priv, dma_conf, queue);
1766 rx_q->buf_alloc_num = 0;
1767 rx_q->xsk_pool = NULL;
1776 * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue)
1777 * @priv: driver private structure
1778 * @dma_conf: structure to take the dma data
1779 * @queue: TX queue index
1780 * Description: this function initializes the DMA TX descriptors
1781 * and allocates the socket buffers. It supports the chained and ring
1784 static int __init_dma_tx_desc_rings(struct stmmac_priv *priv,
1785 struct stmmac_dma_conf *dma_conf,
1788 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue];
1791 netif_dbg(priv, probe, priv->dev,
1792 "(%s) dma_tx_phy=0x%08x\n", __func__,
1793 (u32)tx_q->dma_tx_phy);
1795 /* Setup the chained descriptor addresses */
1796 if (priv->mode == STMMAC_CHAIN_MODE) {
1797 if (priv->extend_desc)
1798 stmmac_mode_init(priv, tx_q->dma_etx,
1800 dma_conf->dma_tx_size, 1);
1801 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL))
1802 stmmac_mode_init(priv, tx_q->dma_tx,
1804 dma_conf->dma_tx_size, 0);
1807 tx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue);
1809 for (i = 0; i < dma_conf->dma_tx_size; i++) {
1812 if (priv->extend_desc)
1813 p = &((tx_q->dma_etx + i)->basic);
1814 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
1815 p = &((tx_q->dma_entx + i)->basic);
1817 p = tx_q->dma_tx + i;
1819 stmmac_clear_desc(priv, p);
1821 tx_q->tx_skbuff_dma[i].buf = 0;
1822 tx_q->tx_skbuff_dma[i].map_as_page = false;
1823 tx_q->tx_skbuff_dma[i].len = 0;
1824 tx_q->tx_skbuff_dma[i].last_segment = false;
1825 tx_q->tx_skbuff[i] = NULL;
1831 static int init_dma_tx_desc_rings(struct net_device *dev,
1832 struct stmmac_dma_conf *dma_conf)
1834 struct stmmac_priv *priv = netdev_priv(dev);
1838 tx_queue_cnt = priv->plat->tx_queues_to_use;
1840 for (queue = 0; queue < tx_queue_cnt; queue++)
1841 __init_dma_tx_desc_rings(priv, dma_conf, queue);
1847 * init_dma_desc_rings - init the RX/TX descriptor rings
1848 * @dev: net device structure
1849 * @dma_conf: structure to take the dma data
1851 * Description: this function initializes the DMA RX/TX descriptors
1852 * and allocates the socket buffers. It supports the chained and ring
1855 static int init_dma_desc_rings(struct net_device *dev,
1856 struct stmmac_dma_conf *dma_conf,
1859 struct stmmac_priv *priv = netdev_priv(dev);
1862 ret = init_dma_rx_desc_rings(dev, dma_conf, flags);
1866 ret = init_dma_tx_desc_rings(dev, dma_conf);
1868 stmmac_clear_descriptors(priv, dma_conf);
1870 if (netif_msg_hw(priv))
1871 stmmac_display_rings(priv, dma_conf);
1877 * dma_free_tx_skbufs - free TX dma buffers
1878 * @priv: private structure
1879 * @dma_conf: structure to take the dma data
1880 * @queue: TX queue index
1882 static void dma_free_tx_skbufs(struct stmmac_priv *priv,
1883 struct stmmac_dma_conf *dma_conf,
1886 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue];
1889 tx_q->xsk_frames_done = 0;
1891 for (i = 0; i < dma_conf->dma_tx_size; i++)
1892 stmmac_free_tx_buffer(priv, dma_conf, queue, i);
1894 if (tx_q->xsk_pool && tx_q->xsk_frames_done) {
1895 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done);
1896 tx_q->xsk_frames_done = 0;
1897 tx_q->xsk_pool = NULL;
1902 * stmmac_free_tx_skbufs - free TX skb buffers
1903 * @priv: private structure
1905 static void stmmac_free_tx_skbufs(struct stmmac_priv *priv)
1907 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1910 for (queue = 0; queue < tx_queue_cnt; queue++)
1911 dma_free_tx_skbufs(priv, &priv->dma_conf, queue);
1915 * __free_dma_rx_desc_resources - free RX dma desc resources (per queue)
1916 * @priv: private structure
1917 * @dma_conf: structure to take the dma data
1918 * @queue: RX queue index
1920 static void __free_dma_rx_desc_resources(struct stmmac_priv *priv,
1921 struct stmmac_dma_conf *dma_conf,
1924 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1926 /* Release the DMA RX socket buffers */
1928 dma_free_rx_xskbufs(priv, dma_conf, queue);
1930 dma_free_rx_skbufs(priv, dma_conf, queue);
1932 rx_q->buf_alloc_num = 0;
1933 rx_q->xsk_pool = NULL;
1935 /* Free DMA regions of consistent memory previously allocated */
1936 if (!priv->extend_desc)
1937 dma_free_coherent(priv->device, dma_conf->dma_rx_size *
1938 sizeof(struct dma_desc),
1939 rx_q->dma_rx, rx_q->dma_rx_phy);
1941 dma_free_coherent(priv->device, dma_conf->dma_rx_size *
1942 sizeof(struct dma_extended_desc),
1943 rx_q->dma_erx, rx_q->dma_rx_phy);
1945 if (xdp_rxq_info_is_reg(&rx_q->xdp_rxq))
1946 xdp_rxq_info_unreg(&rx_q->xdp_rxq);
1948 kfree(rx_q->buf_pool);
1949 if (rx_q->page_pool)
1950 page_pool_destroy(rx_q->page_pool);
1953 static void free_dma_rx_desc_resources(struct stmmac_priv *priv,
1954 struct stmmac_dma_conf *dma_conf)
1956 u32 rx_count = priv->plat->rx_queues_to_use;
1959 /* Free RX queue resources */
1960 for (queue = 0; queue < rx_count; queue++)
1961 __free_dma_rx_desc_resources(priv, dma_conf, queue);
1965 * __free_dma_tx_desc_resources - free TX dma desc resources (per queue)
1966 * @priv: private structure
1967 * @dma_conf: structure to take the dma data
1968 * @queue: TX queue index
1970 static void __free_dma_tx_desc_resources(struct stmmac_priv *priv,
1971 struct stmmac_dma_conf *dma_conf,
1974 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue];
1978 /* Release the DMA TX socket buffers */
1979 dma_free_tx_skbufs(priv, dma_conf, queue);
1981 if (priv->extend_desc) {
1982 size = sizeof(struct dma_extended_desc);
1983 addr = tx_q->dma_etx;
1984 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) {
1985 size = sizeof(struct dma_edesc);
1986 addr = tx_q->dma_entx;
1988 size = sizeof(struct dma_desc);
1989 addr = tx_q->dma_tx;
1992 size *= dma_conf->dma_tx_size;
1994 dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy);
1996 kfree(tx_q->tx_skbuff_dma);
1997 kfree(tx_q->tx_skbuff);
2000 static void free_dma_tx_desc_resources(struct stmmac_priv *priv,
2001 struct stmmac_dma_conf *dma_conf)
2003 u32 tx_count = priv->plat->tx_queues_to_use;
2006 /* Free TX queue resources */
2007 for (queue = 0; queue < tx_count; queue++)
2008 __free_dma_tx_desc_resources(priv, dma_conf, queue);
2012 * __alloc_dma_rx_desc_resources - alloc RX resources (per queue).
2013 * @priv: private structure
2014 * @dma_conf: structure to take the dma data
2015 * @queue: RX queue index
2016 * Description: according to which descriptor can be used (extend or basic)
2017 * this function allocates the resources for TX and RX paths. In case of
2018 * reception, for example, it pre-allocated the RX socket buffer in order to
2019 * allow zero-copy mechanism.
2021 static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv,
2022 struct stmmac_dma_conf *dma_conf,
2025 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
2026 struct stmmac_channel *ch = &priv->channel[queue];
2027 bool xdp_prog = stmmac_xdp_is_enabled(priv);
2028 struct page_pool_params pp_params = { 0 };
2029 unsigned int num_pages;
2030 unsigned int napi_id;
2033 rx_q->queue_index = queue;
2034 rx_q->priv_data = priv;
2036 pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV;
2037 pp_params.pool_size = dma_conf->dma_rx_size;
2038 num_pages = DIV_ROUND_UP(dma_conf->dma_buf_sz, PAGE_SIZE);
2039 pp_params.order = ilog2(num_pages);
2040 pp_params.nid = dev_to_node(priv->device);
2041 pp_params.dev = priv->device;
2042 pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
2043 pp_params.offset = stmmac_rx_offset(priv);
2044 pp_params.max_len = STMMAC_MAX_RX_BUF_SIZE(num_pages);
2046 rx_q->page_pool = page_pool_create(&pp_params);
2047 if (IS_ERR(rx_q->page_pool)) {
2048 ret = PTR_ERR(rx_q->page_pool);
2049 rx_q->page_pool = NULL;
2053 rx_q->buf_pool = kcalloc(dma_conf->dma_rx_size,
2054 sizeof(*rx_q->buf_pool),
2056 if (!rx_q->buf_pool)
2059 if (priv->extend_desc) {
2060 rx_q->dma_erx = dma_alloc_coherent(priv->device,
2061 dma_conf->dma_rx_size *
2062 sizeof(struct dma_extended_desc),
2069 rx_q->dma_rx = dma_alloc_coherent(priv->device,
2070 dma_conf->dma_rx_size *
2071 sizeof(struct dma_desc),
2078 if (stmmac_xdp_is_enabled(priv) &&
2079 test_bit(queue, priv->af_xdp_zc_qps))
2080 napi_id = ch->rxtx_napi.napi_id;
2082 napi_id = ch->rx_napi.napi_id;
2084 ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev,
2088 netdev_err(priv->dev, "Failed to register xdp rxq info\n");
2095 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv,
2096 struct stmmac_dma_conf *dma_conf)
2098 u32 rx_count = priv->plat->rx_queues_to_use;
2102 /* RX queues buffers and DMA */
2103 for (queue = 0; queue < rx_count; queue++) {
2104 ret = __alloc_dma_rx_desc_resources(priv, dma_conf, queue);
2112 free_dma_rx_desc_resources(priv, dma_conf);
2118 * __alloc_dma_tx_desc_resources - alloc TX resources (per queue).
2119 * @priv: private structure
2120 * @dma_conf: structure to take the dma data
2121 * @queue: TX queue index
2122 * Description: according to which descriptor can be used (extend or basic)
2123 * this function allocates the resources for TX and RX paths. In case of
2124 * reception, for example, it pre-allocated the RX socket buffer in order to
2125 * allow zero-copy mechanism.
2127 static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv,
2128 struct stmmac_dma_conf *dma_conf,
2131 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue];
2135 tx_q->queue_index = queue;
2136 tx_q->priv_data = priv;
2138 tx_q->tx_skbuff_dma = kcalloc(dma_conf->dma_tx_size,
2139 sizeof(*tx_q->tx_skbuff_dma),
2141 if (!tx_q->tx_skbuff_dma)
2144 tx_q->tx_skbuff = kcalloc(dma_conf->dma_tx_size,
2145 sizeof(struct sk_buff *),
2147 if (!tx_q->tx_skbuff)
2150 if (priv->extend_desc)
2151 size = sizeof(struct dma_extended_desc);
2152 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2153 size = sizeof(struct dma_edesc);
2155 size = sizeof(struct dma_desc);
2157 size *= dma_conf->dma_tx_size;
2159 addr = dma_alloc_coherent(priv->device, size,
2160 &tx_q->dma_tx_phy, GFP_KERNEL);
2164 if (priv->extend_desc)
2165 tx_q->dma_etx = addr;
2166 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2167 tx_q->dma_entx = addr;
2169 tx_q->dma_tx = addr;
2174 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv,
2175 struct stmmac_dma_conf *dma_conf)
2177 u32 tx_count = priv->plat->tx_queues_to_use;
2181 /* TX queues buffers and DMA */
2182 for (queue = 0; queue < tx_count; queue++) {
2183 ret = __alloc_dma_tx_desc_resources(priv, dma_conf, queue);
2191 free_dma_tx_desc_resources(priv, dma_conf);
2196 * alloc_dma_desc_resources - alloc TX/RX resources.
2197 * @priv: private structure
2198 * @dma_conf: structure to take the dma data
2199 * Description: according to which descriptor can be used (extend or basic)
2200 * this function allocates the resources for TX and RX paths. In case of
2201 * reception, for example, it pre-allocated the RX socket buffer in order to
2202 * allow zero-copy mechanism.
2204 static int alloc_dma_desc_resources(struct stmmac_priv *priv,
2205 struct stmmac_dma_conf *dma_conf)
2208 int ret = alloc_dma_rx_desc_resources(priv, dma_conf);
2213 ret = alloc_dma_tx_desc_resources(priv, dma_conf);
2219 * free_dma_desc_resources - free dma desc resources
2220 * @priv: private structure
2221 * @dma_conf: structure to take the dma data
2223 static void free_dma_desc_resources(struct stmmac_priv *priv,
2224 struct stmmac_dma_conf *dma_conf)
2226 /* Release the DMA TX socket buffers */
2227 free_dma_tx_desc_resources(priv, dma_conf);
2229 /* Release the DMA RX socket buffers later
2230 * to ensure all pending XDP_TX buffers are returned.
2232 free_dma_rx_desc_resources(priv, dma_conf);
2236 * stmmac_mac_enable_rx_queues - Enable MAC rx queues
2237 * @priv: driver private structure
2238 * Description: It is used for enabling the rx queues in the MAC
2240 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
2242 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2246 for (queue = 0; queue < rx_queues_count; queue++) {
2247 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
2248 stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
2253 * stmmac_start_rx_dma - start RX DMA channel
2254 * @priv: driver private structure
2255 * @chan: RX channel index
2257 * This starts a RX DMA channel
2259 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
2261 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
2262 stmmac_start_rx(priv, priv->ioaddr, chan);
2266 * stmmac_start_tx_dma - start TX DMA channel
2267 * @priv: driver private structure
2268 * @chan: TX channel index
2270 * This starts a TX DMA channel
2272 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
2274 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
2275 stmmac_start_tx(priv, priv->ioaddr, chan);
2279 * stmmac_stop_rx_dma - stop RX DMA channel
2280 * @priv: driver private structure
2281 * @chan: RX channel index
2283 * This stops a RX DMA channel
2285 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
2287 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
2288 stmmac_stop_rx(priv, priv->ioaddr, chan);
2292 * stmmac_stop_tx_dma - stop TX DMA channel
2293 * @priv: driver private structure
2294 * @chan: TX channel index
2296 * This stops a TX DMA channel
2298 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
2300 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
2301 stmmac_stop_tx(priv, priv->ioaddr, chan);
2304 static void stmmac_enable_all_dma_irq(struct stmmac_priv *priv)
2306 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2307 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2308 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2311 for (chan = 0; chan < dma_csr_ch; chan++) {
2312 struct stmmac_channel *ch = &priv->channel[chan];
2313 unsigned long flags;
2315 spin_lock_irqsave(&ch->lock, flags);
2316 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1);
2317 spin_unlock_irqrestore(&ch->lock, flags);
2322 * stmmac_start_all_dma - start all RX and TX DMA channels
2323 * @priv: driver private structure
2325 * This starts all the RX and TX DMA channels
2327 static void stmmac_start_all_dma(struct stmmac_priv *priv)
2329 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2330 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2333 for (chan = 0; chan < rx_channels_count; chan++)
2334 stmmac_start_rx_dma(priv, chan);
2336 for (chan = 0; chan < tx_channels_count; chan++)
2337 stmmac_start_tx_dma(priv, chan);
2341 * stmmac_stop_all_dma - stop all RX and TX DMA channels
2342 * @priv: driver private structure
2344 * This stops the RX and TX DMA channels
2346 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
2348 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2349 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2352 for (chan = 0; chan < rx_channels_count; chan++)
2353 stmmac_stop_rx_dma(priv, chan);
2355 for (chan = 0; chan < tx_channels_count; chan++)
2356 stmmac_stop_tx_dma(priv, chan);
2360 * stmmac_dma_operation_mode - HW DMA operation mode
2361 * @priv: driver private structure
2362 * Description: it is used for configuring the DMA operation mode register in
2363 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
2365 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
2367 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2368 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2369 int rxfifosz = priv->plat->rx_fifo_size;
2370 int txfifosz = priv->plat->tx_fifo_size;
2377 rxfifosz = priv->dma_cap.rx_fifo_size;
2379 txfifosz = priv->dma_cap.tx_fifo_size;
2381 /* Adjust for real per queue fifo size */
2382 rxfifosz /= rx_channels_count;
2383 txfifosz /= tx_channels_count;
2385 if (priv->plat->force_thresh_dma_mode) {
2388 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
2390 * In case of GMAC, SF mode can be enabled
2391 * to perform the TX COE in HW. This depends on:
2392 * 1) TX COE if actually supported
2393 * 2) There is no bugged Jumbo frame support
2394 * that needs to not insert csum in the TDES.
2396 txmode = SF_DMA_MODE;
2397 rxmode = SF_DMA_MODE;
2398 priv->xstats.threshold = SF_DMA_MODE;
2401 rxmode = SF_DMA_MODE;
2404 /* configure all channels */
2405 for (chan = 0; chan < rx_channels_count; chan++) {
2406 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[chan];
2409 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2411 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
2414 if (rx_q->xsk_pool) {
2415 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool);
2416 stmmac_set_dma_bfsize(priv, priv->ioaddr,
2420 stmmac_set_dma_bfsize(priv, priv->ioaddr,
2421 priv->dma_conf.dma_buf_sz,
2426 for (chan = 0; chan < tx_channels_count; chan++) {
2427 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2429 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
2434 static void stmmac_xsk_request_timestamp(void *_priv)
2436 struct stmmac_metadata_request *meta_req = _priv;
2438 stmmac_enable_tx_timestamp(meta_req->priv, meta_req->tx_desc);
2439 *meta_req->set_ic = true;
2442 static u64 stmmac_xsk_fill_timestamp(void *_priv)
2444 struct stmmac_xsk_tx_complete *tx_compl = _priv;
2445 struct stmmac_priv *priv = tx_compl->priv;
2446 struct dma_desc *desc = tx_compl->desc;
2450 if (!priv->hwts_tx_en)
2453 /* check tx tstamp status */
2454 if (stmmac_get_tx_timestamp_status(priv, desc)) {
2455 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
2457 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) {
2462 ns -= priv->plat->cdc_error_adj;
2463 return ns_to_ktime(ns);
2469 static const struct xsk_tx_metadata_ops stmmac_xsk_tx_metadata_ops = {
2470 .tmo_request_timestamp = stmmac_xsk_request_timestamp,
2471 .tmo_fill_timestamp = stmmac_xsk_fill_timestamp,
2474 static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
2476 struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue);
2477 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
2478 struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[queue];
2479 struct xsk_buff_pool *pool = tx_q->xsk_pool;
2480 unsigned int entry = tx_q->cur_tx;
2481 struct dma_desc *tx_desc = NULL;
2482 struct xdp_desc xdp_desc;
2483 bool work_done = true;
2484 u32 tx_set_ic_bit = 0;
2485 unsigned long flags;
2487 /* Avoids TX time-out as we are sharing with slow path */
2488 txq_trans_cond_update(nq);
2490 budget = min(budget, stmmac_tx_avail(priv, queue));
2492 while (budget-- > 0) {
2493 struct stmmac_metadata_request meta_req;
2494 struct xsk_tx_metadata *meta = NULL;
2495 dma_addr_t dma_addr;
2498 /* We are sharing with slow path and stop XSK TX desc submission when
2499 * available TX ring is less than threshold.
2501 if (unlikely(stmmac_tx_avail(priv, queue) < STMMAC_TX_XSK_AVAIL) ||
2502 !netif_carrier_ok(priv->dev)) {
2507 if (!xsk_tx_peek_desc(pool, &xdp_desc))
2510 if (likely(priv->extend_desc))
2511 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry);
2512 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2513 tx_desc = &tx_q->dma_entx[entry].basic;
2515 tx_desc = tx_q->dma_tx + entry;
2517 dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr);
2518 meta = xsk_buff_get_metadata(pool, xdp_desc.addr);
2519 xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len);
2521 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX;
2523 /* To return XDP buffer to XSK pool, we simple call
2524 * xsk_tx_completed(), so we don't need to fill up
2527 tx_q->tx_skbuff_dma[entry].buf = 0;
2528 tx_q->xdpf[entry] = NULL;
2530 tx_q->tx_skbuff_dma[entry].map_as_page = false;
2531 tx_q->tx_skbuff_dma[entry].len = xdp_desc.len;
2532 tx_q->tx_skbuff_dma[entry].last_segment = true;
2533 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
2535 stmmac_set_desc_addr(priv, tx_desc, dma_addr);
2537 tx_q->tx_count_frames++;
2539 if (!priv->tx_coal_frames[queue])
2541 else if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0)
2546 meta_req.priv = priv;
2547 meta_req.tx_desc = tx_desc;
2548 meta_req.set_ic = &set_ic;
2549 xsk_tx_metadata_request(meta, &stmmac_xsk_tx_metadata_ops,
2552 tx_q->tx_count_frames = 0;
2553 stmmac_set_tx_ic(priv, tx_desc);
2557 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len,
2558 true, priv->mode, true, true,
2561 stmmac_enable_dma_transmission(priv, priv->ioaddr);
2563 xsk_tx_metadata_to_compl(meta,
2564 &tx_q->tx_skbuff_dma[entry].xsk_meta);
2566 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size);
2567 entry = tx_q->cur_tx;
2569 flags = u64_stats_update_begin_irqsave(&txq_stats->syncp);
2570 txq_stats->tx_set_ic_bit += tx_set_ic_bit;
2571 u64_stats_update_end_irqrestore(&txq_stats->syncp, flags);
2574 stmmac_flush_tx_descriptors(priv, queue);
2575 xsk_tx_release(pool);
2578 /* Return true if all of the 3 conditions are met
2579 * a) TX Budget is still available
2580 * b) work_done = true when XSK TX desc peek is empty (no more
2581 * pending XSK TX for transmission)
2583 return !!budget && work_done;
2586 static void stmmac_bump_dma_threshold(struct stmmac_priv *priv, u32 chan)
2588 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && tc <= 256) {
2591 if (priv->plat->force_thresh_dma_mode)
2592 stmmac_set_dma_operation_mode(priv, tc, tc, chan);
2594 stmmac_set_dma_operation_mode(priv, tc, SF_DMA_MODE,
2597 priv->xstats.threshold = tc;
2602 * stmmac_tx_clean - to manage the transmission completion
2603 * @priv: driver private structure
2604 * @budget: napi budget limiting this functions packet handling
2605 * @queue: TX queue index
2606 * @pending_packets: signal to arm the TX coal timer
2607 * Description: it reclaims the transmit resources after transmission completes.
2608 * If some packets still needs to be handled, due to TX coalesce, set
2609 * pending_packets to true to make NAPI arm the TX coal timer.
2611 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue,
2612 bool *pending_packets)
2614 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
2615 struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[queue];
2616 unsigned int bytes_compl = 0, pkts_compl = 0;
2617 unsigned int entry, xmits = 0, count = 0;
2618 u32 tx_packets = 0, tx_errors = 0;
2619 unsigned long flags;
2621 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue));
2623 tx_q->xsk_frames_done = 0;
2625 entry = tx_q->dirty_tx;
2627 /* Try to clean all TX complete frame in 1 shot */
2628 while ((entry != tx_q->cur_tx) && count < priv->dma_conf.dma_tx_size) {
2629 struct xdp_frame *xdpf;
2630 struct sk_buff *skb;
2634 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX ||
2635 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) {
2636 xdpf = tx_q->xdpf[entry];
2638 } else if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) {
2640 skb = tx_q->tx_skbuff[entry];
2646 if (priv->extend_desc)
2647 p = (struct dma_desc *)(tx_q->dma_etx + entry);
2648 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2649 p = &tx_q->dma_entx[entry].basic;
2651 p = tx_q->dma_tx + entry;
2653 status = stmmac_tx_status(priv, &priv->xstats, p, priv->ioaddr);
2654 /* Check if the descriptor is owned by the DMA */
2655 if (unlikely(status & tx_dma_own))
2660 /* Make sure descriptor fields are read after reading
2665 /* Just consider the last segment and ...*/
2666 if (likely(!(status & tx_not_ls))) {
2667 /* ... verify the status error condition */
2668 if (unlikely(status & tx_err)) {
2670 if (unlikely(status & tx_err_bump_tc))
2671 stmmac_bump_dma_threshold(priv, queue);
2676 stmmac_get_tx_hwtstamp(priv, p, skb);
2678 struct stmmac_xsk_tx_complete tx_compl = {
2683 xsk_tx_metadata_complete(&tx_q->tx_skbuff_dma[entry].xsk_meta,
2684 &stmmac_xsk_tx_metadata_ops,
2689 if (likely(tx_q->tx_skbuff_dma[entry].buf &&
2690 tx_q->tx_skbuff_dma[entry].buf_type != STMMAC_TXBUF_T_XDP_TX)) {
2691 if (tx_q->tx_skbuff_dma[entry].map_as_page)
2692 dma_unmap_page(priv->device,
2693 tx_q->tx_skbuff_dma[entry].buf,
2694 tx_q->tx_skbuff_dma[entry].len,
2697 dma_unmap_single(priv->device,
2698 tx_q->tx_skbuff_dma[entry].buf,
2699 tx_q->tx_skbuff_dma[entry].len,
2701 tx_q->tx_skbuff_dma[entry].buf = 0;
2702 tx_q->tx_skbuff_dma[entry].len = 0;
2703 tx_q->tx_skbuff_dma[entry].map_as_page = false;
2706 stmmac_clean_desc3(priv, tx_q, p);
2708 tx_q->tx_skbuff_dma[entry].last_segment = false;
2709 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
2712 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX) {
2713 xdp_return_frame_rx_napi(xdpf);
2714 tx_q->xdpf[entry] = NULL;
2718 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) {
2719 xdp_return_frame(xdpf);
2720 tx_q->xdpf[entry] = NULL;
2723 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XSK_TX)
2724 tx_q->xsk_frames_done++;
2726 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) {
2729 bytes_compl += skb->len;
2730 dev_consume_skb_any(skb);
2731 tx_q->tx_skbuff[entry] = NULL;
2735 stmmac_release_tx_desc(priv, p, priv->mode);
2737 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size);
2739 tx_q->dirty_tx = entry;
2741 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
2742 pkts_compl, bytes_compl);
2744 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
2746 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) {
2748 netif_dbg(priv, tx_done, priv->dev,
2749 "%s: restart transmit\n", __func__);
2750 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
2753 if (tx_q->xsk_pool) {
2756 if (tx_q->xsk_frames_done)
2757 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done);
2759 if (xsk_uses_need_wakeup(tx_q->xsk_pool))
2760 xsk_set_tx_need_wakeup(tx_q->xsk_pool);
2762 /* For XSK TX, we try to send as many as possible.
2763 * If XSK work done (XSK TX desc empty and budget still
2764 * available), return "budget - 1" to reenable TX IRQ.
2765 * Else, return "budget" to make NAPI continue polling.
2767 work_done = stmmac_xdp_xmit_zc(priv, queue,
2768 STMMAC_XSK_TX_BUDGET_MAX);
2775 if (priv->eee_enabled && !priv->tx_path_in_lpi_mode &&
2776 priv->eee_sw_timer_en) {
2777 if (stmmac_enable_eee_mode(priv))
2778 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer));
2781 /* We still have pending packets, let's call for a new scheduling */
2782 if (tx_q->dirty_tx != tx_q->cur_tx)
2783 *pending_packets = true;
2785 flags = u64_stats_update_begin_irqsave(&txq_stats->syncp);
2786 txq_stats->tx_packets += tx_packets;
2787 txq_stats->tx_pkt_n += tx_packets;
2788 txq_stats->tx_clean++;
2789 u64_stats_update_end_irqrestore(&txq_stats->syncp, flags);
2791 priv->xstats.tx_errors += tx_errors;
2793 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
2795 /* Combine decisions from TX clean and XSK TX */
2796 return max(count, xmits);
2800 * stmmac_tx_err - to manage the tx error
2801 * @priv: driver private structure
2802 * @chan: channel index
2803 * Description: it cleans the descriptors and restarts the transmission
2804 * in case of transmission errors.
2806 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
2808 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan];
2810 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
2812 stmmac_stop_tx_dma(priv, chan);
2813 dma_free_tx_skbufs(priv, &priv->dma_conf, chan);
2814 stmmac_clear_tx_descriptors(priv, &priv->dma_conf, chan);
2815 stmmac_reset_tx_queue(priv, chan);
2816 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2817 tx_q->dma_tx_phy, chan);
2818 stmmac_start_tx_dma(priv, chan);
2820 priv->xstats.tx_errors++;
2821 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
2825 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel
2826 * @priv: driver private structure
2827 * @txmode: TX operating mode
2828 * @rxmode: RX operating mode
2829 * @chan: channel index
2830 * Description: it is used for configuring of the DMA operation mode in
2831 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
2834 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
2835 u32 rxmode, u32 chan)
2837 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2838 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2839 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2840 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2841 int rxfifosz = priv->plat->rx_fifo_size;
2842 int txfifosz = priv->plat->tx_fifo_size;
2845 rxfifosz = priv->dma_cap.rx_fifo_size;
2847 txfifosz = priv->dma_cap.tx_fifo_size;
2849 /* Adjust for real per queue fifo size */
2850 rxfifosz /= rx_channels_count;
2851 txfifosz /= tx_channels_count;
2853 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode);
2854 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode);
2857 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
2861 ret = stmmac_safety_feat_irq_status(priv, priv->dev,
2862 priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
2863 if (ret && (ret != -EINVAL)) {
2864 stmmac_global_err(priv);
2871 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan, u32 dir)
2873 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
2874 &priv->xstats, chan, dir);
2875 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[chan];
2876 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan];
2877 struct stmmac_channel *ch = &priv->channel[chan];
2878 struct napi_struct *rx_napi;
2879 struct napi_struct *tx_napi;
2880 unsigned long flags;
2882 rx_napi = rx_q->xsk_pool ? &ch->rxtx_napi : &ch->rx_napi;
2883 tx_napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi;
2885 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
2886 if (napi_schedule_prep(rx_napi)) {
2887 spin_lock_irqsave(&ch->lock, flags);
2888 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0);
2889 spin_unlock_irqrestore(&ch->lock, flags);
2890 __napi_schedule(rx_napi);
2894 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) {
2895 if (napi_schedule_prep(tx_napi)) {
2896 spin_lock_irqsave(&ch->lock, flags);
2897 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1);
2898 spin_unlock_irqrestore(&ch->lock, flags);
2899 __napi_schedule(tx_napi);
2907 * stmmac_dma_interrupt - DMA ISR
2908 * @priv: driver private structure
2909 * Description: this is the DMA ISR. It is called by the main ISR.
2910 * It calls the dwmac dma routine and schedule poll method in case of some
2913 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
2915 u32 tx_channel_count = priv->plat->tx_queues_to_use;
2916 u32 rx_channel_count = priv->plat->rx_queues_to_use;
2917 u32 channels_to_check = tx_channel_count > rx_channel_count ?
2918 tx_channel_count : rx_channel_count;
2920 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
2922 /* Make sure we never check beyond our status buffer. */
2923 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
2924 channels_to_check = ARRAY_SIZE(status);
2926 for (chan = 0; chan < channels_to_check; chan++)
2927 status[chan] = stmmac_napi_check(priv, chan,
2930 for (chan = 0; chan < tx_channel_count; chan++) {
2931 if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
2932 /* Try to bump up the dma threshold on this failure */
2933 stmmac_bump_dma_threshold(priv, chan);
2934 } else if (unlikely(status[chan] == tx_hard_error)) {
2935 stmmac_tx_err(priv, chan);
2941 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2942 * @priv: driver private structure
2943 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2945 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2947 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2948 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2950 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr);
2952 if (priv->dma_cap.rmon) {
2953 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode);
2954 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2956 netdev_info(priv->dev, "No MAC Management Counters available\n");
2960 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2961 * @priv: driver private structure
2963 * new GMAC chip generations have a new register to indicate the
2964 * presence of the optional feature/functions.
2965 * This can be also used to override the value passed through the
2966 * platform and necessary for old MAC10/100 and GMAC chips.
2968 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2970 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
2974 * stmmac_check_ether_addr - check if the MAC addr is valid
2975 * @priv: driver private structure
2977 * it is to verify if the MAC address is valid, in case of failures it
2978 * generates a random MAC address
2980 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2984 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2985 stmmac_get_umac_addr(priv, priv->hw, addr, 0);
2986 if (is_valid_ether_addr(addr))
2987 eth_hw_addr_set(priv->dev, addr);
2989 eth_hw_addr_random(priv->dev);
2990 dev_info(priv->device, "device MAC address %pM\n",
2991 priv->dev->dev_addr);
2996 * stmmac_init_dma_engine - DMA init.
2997 * @priv: driver private structure
2999 * It inits the DMA invoking the specific MAC/GMAC callback.
3000 * Some DMA parameters can be passed from the platform;
3001 * in case of these are not passed a default is kept for the MAC or GMAC.
3003 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
3005 u32 rx_channels_count = priv->plat->rx_queues_to_use;
3006 u32 tx_channels_count = priv->plat->tx_queues_to_use;
3007 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
3008 struct stmmac_rx_queue *rx_q;
3009 struct stmmac_tx_queue *tx_q;
3014 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
3015 dev_err(priv->device, "Invalid DMA configuration\n");
3019 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
3022 ret = stmmac_reset(priv, priv->ioaddr);
3024 dev_err(priv->device, "Failed to reset the dma\n");
3028 /* DMA Configuration */
3029 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);
3031 if (priv->plat->axi)
3032 stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
3034 /* DMA CSR Channel configuration */
3035 for (chan = 0; chan < dma_csr_ch; chan++) {
3036 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
3037 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1);
3040 /* DMA RX Channel Configuration */
3041 for (chan = 0; chan < rx_channels_count; chan++) {
3042 rx_q = &priv->dma_conf.rx_queue[chan];
3044 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
3045 rx_q->dma_rx_phy, chan);
3047 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
3048 (rx_q->buf_alloc_num *
3049 sizeof(struct dma_desc));
3050 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
3051 rx_q->rx_tail_addr, chan);
3054 /* DMA TX Channel Configuration */
3055 for (chan = 0; chan < tx_channels_count; chan++) {
3056 tx_q = &priv->dma_conf.tx_queue[chan];
3058 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
3059 tx_q->dma_tx_phy, chan);
3061 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
3062 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
3063 tx_q->tx_tail_addr, chan);
3069 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
3071 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
3072 u32 tx_coal_timer = priv->tx_coal_timer[queue];
3073 struct stmmac_channel *ch;
3074 struct napi_struct *napi;
3079 ch = &priv->channel[tx_q->queue_index];
3080 napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi;
3082 /* Arm timer only if napi is not already scheduled.
3083 * Try to cancel any timer if napi is scheduled, timer will be armed
3084 * again in the next scheduled napi.
3086 if (unlikely(!napi_is_scheduled(napi)))
3087 hrtimer_start(&tx_q->txtimer,
3088 STMMAC_COAL_TIMER(tx_coal_timer),
3091 hrtimer_try_to_cancel(&tx_q->txtimer);
3095 * stmmac_tx_timer - mitigation sw timer for tx.
3098 * This is the timer handler to directly invoke the stmmac_tx_clean.
3100 static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t)
3102 struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer);
3103 struct stmmac_priv *priv = tx_q->priv_data;
3104 struct stmmac_channel *ch;
3105 struct napi_struct *napi;
3107 ch = &priv->channel[tx_q->queue_index];
3108 napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi;
3110 if (likely(napi_schedule_prep(napi))) {
3111 unsigned long flags;
3113 spin_lock_irqsave(&ch->lock, flags);
3114 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1);
3115 spin_unlock_irqrestore(&ch->lock, flags);
3116 __napi_schedule(napi);
3119 return HRTIMER_NORESTART;
3123 * stmmac_init_coalesce - init mitigation options.
3124 * @priv: driver private structure
3126 * This inits the coalesce parameters: i.e. timer rate,
3127 * timer handler and default threshold used for enabling the
3128 * interrupt on completion bit.
3130 static void stmmac_init_coalesce(struct stmmac_priv *priv)
3132 u32 tx_channel_count = priv->plat->tx_queues_to_use;
3133 u32 rx_channel_count = priv->plat->rx_queues_to_use;
3136 for (chan = 0; chan < tx_channel_count; chan++) {
3137 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan];
3139 priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES;
3140 priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER;
3142 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
3143 tx_q->txtimer.function = stmmac_tx_timer;
3146 for (chan = 0; chan < rx_channel_count; chan++)
3147 priv->rx_coal_frames[chan] = STMMAC_RX_FRAMES;
3150 static void stmmac_set_rings_length(struct stmmac_priv *priv)
3152 u32 rx_channels_count = priv->plat->rx_queues_to_use;
3153 u32 tx_channels_count = priv->plat->tx_queues_to_use;
3156 /* set TX ring length */
3157 for (chan = 0; chan < tx_channels_count; chan++)
3158 stmmac_set_tx_ring_len(priv, priv->ioaddr,
3159 (priv->dma_conf.dma_tx_size - 1), chan);
3161 /* set RX ring length */
3162 for (chan = 0; chan < rx_channels_count; chan++)
3163 stmmac_set_rx_ring_len(priv, priv->ioaddr,
3164 (priv->dma_conf.dma_rx_size - 1), chan);
3168 * stmmac_set_tx_queue_weight - Set TX queue weight
3169 * @priv: driver private structure
3170 * Description: It is used for setting TX queues weight
3172 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
3174 u32 tx_queues_count = priv->plat->tx_queues_to_use;
3178 for (queue = 0; queue < tx_queues_count; queue++) {
3179 weight = priv->plat->tx_queues_cfg[queue].weight;
3180 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue);
3185 * stmmac_configure_cbs - Configure CBS in TX queue
3186 * @priv: driver private structure
3187 * Description: It is used for configuring CBS in AVB TX queues
3189 static void stmmac_configure_cbs(struct stmmac_priv *priv)
3191 u32 tx_queues_count = priv->plat->tx_queues_to_use;
3195 /* queue 0 is reserved for legacy traffic */
3196 for (queue = 1; queue < tx_queues_count; queue++) {
3197 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
3198 if (mode_to_use == MTL_QUEUE_DCB)
3201 stmmac_config_cbs(priv, priv->hw,
3202 priv->plat->tx_queues_cfg[queue].send_slope,
3203 priv->plat->tx_queues_cfg[queue].idle_slope,
3204 priv->plat->tx_queues_cfg[queue].high_credit,
3205 priv->plat->tx_queues_cfg[queue].low_credit,
3211 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
3212 * @priv: driver private structure
3213 * Description: It is used for mapping RX queues to RX dma channels
3215 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
3217 u32 rx_queues_count = priv->plat->rx_queues_to_use;
3221 for (queue = 0; queue < rx_queues_count; queue++) {
3222 chan = priv->plat->rx_queues_cfg[queue].chan;
3223 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
3228 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
3229 * @priv: driver private structure
3230 * Description: It is used for configuring the RX Queue Priority
3232 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
3234 u32 rx_queues_count = priv->plat->rx_queues_to_use;
3238 for (queue = 0; queue < rx_queues_count; queue++) {
3239 if (!priv->plat->rx_queues_cfg[queue].use_prio)
3242 prio = priv->plat->rx_queues_cfg[queue].prio;
3243 stmmac_rx_queue_prio(priv, priv->hw, prio, queue);
3248 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
3249 * @priv: driver private structure
3250 * Description: It is used for configuring the TX Queue Priority
3252 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
3254 u32 tx_queues_count = priv->plat->tx_queues_to_use;
3258 for (queue = 0; queue < tx_queues_count; queue++) {
3259 if (!priv->plat->tx_queues_cfg[queue].use_prio)
3262 prio = priv->plat->tx_queues_cfg[queue].prio;
3263 stmmac_tx_queue_prio(priv, priv->hw, prio, queue);
3268 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
3269 * @priv: driver private structure
3270 * Description: It is used for configuring the RX queue routing
3272 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
3274 u32 rx_queues_count = priv->plat->rx_queues_to_use;
3278 for (queue = 0; queue < rx_queues_count; queue++) {
3279 /* no specific packet type routing specified for the queue */
3280 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
3283 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
3284 stmmac_rx_queue_routing(priv, priv->hw, packet, queue);
3288 static void stmmac_mac_config_rss(struct stmmac_priv *priv)
3290 if (!priv->dma_cap.rssen || !priv->plat->rss_en) {
3291 priv->rss.enable = false;
3295 if (priv->dev->features & NETIF_F_RXHASH)
3296 priv->rss.enable = true;
3298 priv->rss.enable = false;
3300 stmmac_rss_configure(priv, priv->hw, &priv->rss,
3301 priv->plat->rx_queues_to_use);
3305 * stmmac_mtl_configuration - Configure MTL
3306 * @priv: driver private structure
3307 * Description: It is used for configurring MTL
3309 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
3311 u32 rx_queues_count = priv->plat->rx_queues_to_use;
3312 u32 tx_queues_count = priv->plat->tx_queues_to_use;
3314 if (tx_queues_count > 1)
3315 stmmac_set_tx_queue_weight(priv);
3317 /* Configure MTL RX algorithms */
3318 if (rx_queues_count > 1)
3319 stmmac_prog_mtl_rx_algorithms(priv, priv->hw,
3320 priv->plat->rx_sched_algorithm);
3322 /* Configure MTL TX algorithms */
3323 if (tx_queues_count > 1)
3324 stmmac_prog_mtl_tx_algorithms(priv, priv->hw,
3325 priv->plat->tx_sched_algorithm);
3327 /* Configure CBS in AVB TX queues */
3328 if (tx_queues_count > 1)
3329 stmmac_configure_cbs(priv);
3331 /* Map RX MTL to DMA channels */
3332 stmmac_rx_queue_dma_chan_map(priv);
3334 /* Enable MAC RX Queues */
3335 stmmac_mac_enable_rx_queues(priv);
3337 /* Set RX priorities */
3338 if (rx_queues_count > 1)
3339 stmmac_mac_config_rx_queues_prio(priv);
3341 /* Set TX priorities */
3342 if (tx_queues_count > 1)
3343 stmmac_mac_config_tx_queues_prio(priv);
3345 /* Set RX routing */
3346 if (rx_queues_count > 1)
3347 stmmac_mac_config_rx_queues_routing(priv);
3349 /* Receive Side Scaling */
3350 if (rx_queues_count > 1)
3351 stmmac_mac_config_rss(priv);
3354 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
3356 if (priv->dma_cap.asp) {
3357 netdev_info(priv->dev, "Enabling Safety Features\n");
3358 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp,
3359 priv->plat->safety_feat_cfg);
3361 netdev_info(priv->dev, "No Safety Features support found\n");
3365 static int stmmac_fpe_start_wq(struct stmmac_priv *priv)
3369 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state);
3370 clear_bit(__FPE_REMOVING, &priv->fpe_task_state);
3372 name = priv->wq_name;
3373 sprintf(name, "%s-fpe", priv->dev->name);
3375 priv->fpe_wq = create_singlethread_workqueue(name);
3376 if (!priv->fpe_wq) {
3377 netdev_err(priv->dev, "%s: Failed to create workqueue\n", name);
3381 netdev_info(priv->dev, "FPE workqueue start");
3387 * stmmac_hw_setup - setup mac in a usable state.
3388 * @dev : pointer to the device structure.
3389 * @ptp_register: register PTP if set
3391 * this is the main function to setup the HW in a usable state because the
3392 * dma engine is reset, the core registers are configured (e.g. AXI,
3393 * Checksum features, timers). The DMA is ready to start receiving and
3396 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3399 static int stmmac_hw_setup(struct net_device *dev, bool ptp_register)
3401 struct stmmac_priv *priv = netdev_priv(dev);
3402 u32 rx_cnt = priv->plat->rx_queues_to_use;
3403 u32 tx_cnt = priv->plat->tx_queues_to_use;
3408 /* DMA initialization and SW reset */
3409 ret = stmmac_init_dma_engine(priv);
3411 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
3416 /* Copy the MAC addr into the HW */
3417 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
3419 /* PS and related bits will be programmed according to the speed */
3420 if (priv->hw->pcs) {
3421 int speed = priv->plat->mac_port_sel_speed;
3423 if ((speed == SPEED_10) || (speed == SPEED_100) ||
3424 (speed == SPEED_1000)) {
3425 priv->hw->ps = speed;
3427 dev_warn(priv->device, "invalid port speed\n");
3432 /* Initialize the MAC Core */
3433 stmmac_core_init(priv, priv->hw, dev);
3436 stmmac_mtl_configuration(priv);
3438 /* Initialize Safety Features */
3439 stmmac_safety_feat_configuration(priv);
3441 ret = stmmac_rx_ipc(priv, priv->hw);
3443 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
3444 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
3445 priv->hw->rx_csum = 0;
3448 /* Enable the MAC Rx/Tx */
3449 stmmac_mac_set(priv, priv->ioaddr, true);
3451 /* Set the HW DMA mode and the COE */
3452 stmmac_dma_operation_mode(priv);
3454 stmmac_mmc_setup(priv);
3457 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
3459 netdev_warn(priv->dev,
3460 "failed to enable PTP reference clock: %pe\n",
3464 ret = stmmac_init_ptp(priv);
3465 if (ret == -EOPNOTSUPP)
3466 netdev_info(priv->dev, "PTP not supported by HW\n");
3468 netdev_warn(priv->dev, "PTP init failed\n");
3469 else if (ptp_register)
3470 stmmac_ptp_register(priv);
3472 priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS;
3474 /* Convert the timer from msec to usec */
3475 if (!priv->tx_lpi_timer)
3476 priv->tx_lpi_timer = eee_timer * 1000;
3478 if (priv->use_riwt) {
3481 for (queue = 0; queue < rx_cnt; queue++) {
3482 if (!priv->rx_riwt[queue])
3483 priv->rx_riwt[queue] = DEF_DMA_RIWT;
3485 stmmac_rx_watchdog(priv, priv->ioaddr,
3486 priv->rx_riwt[queue], queue);
3491 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0);
3493 /* set TX and RX rings length */
3494 stmmac_set_rings_length(priv);
3498 for (chan = 0; chan < tx_cnt; chan++) {
3499 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan];
3501 /* TSO and TBS cannot co-exist */
3502 if (tx_q->tbs & STMMAC_TBS_AVAIL)
3505 stmmac_enable_tso(priv, priv->ioaddr, 1, chan);
3509 /* Enable Split Header */
3510 sph_en = (priv->hw->rx_csum > 0) && priv->sph;
3511 for (chan = 0; chan < rx_cnt; chan++)
3512 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
3515 /* VLAN Tag Insertion */
3516 if (priv->dma_cap.vlins)
3517 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT);
3520 for (chan = 0; chan < tx_cnt; chan++) {
3521 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan];
3522 int enable = tx_q->tbs & STMMAC_TBS_AVAIL;
3524 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan);
3527 /* Configure real RX and TX queues */
3528 netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use);
3529 netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use);
3531 /* Start the ball rolling... */
3532 stmmac_start_all_dma(priv);
3534 stmmac_set_hw_vlan_mode(priv, priv->hw);
3536 if (priv->dma_cap.fpesel) {
3537 stmmac_fpe_start_wq(priv);
3539 if (priv->plat->fpe_cfg->enable)
3540 stmmac_fpe_handshake(priv, true);
3546 static void stmmac_hw_teardown(struct net_device *dev)
3548 struct stmmac_priv *priv = netdev_priv(dev);
3550 clk_disable_unprepare(priv->plat->clk_ptp_ref);
3553 static void stmmac_free_irq(struct net_device *dev,
3554 enum request_irq_err irq_err, int irq_idx)
3556 struct stmmac_priv *priv = netdev_priv(dev);
3560 case REQ_IRQ_ERR_ALL:
3561 irq_idx = priv->plat->tx_queues_to_use;
3563 case REQ_IRQ_ERR_TX:
3564 for (j = irq_idx - 1; j >= 0; j--) {
3565 if (priv->tx_irq[j] > 0) {
3566 irq_set_affinity_hint(priv->tx_irq[j], NULL);
3567 free_irq(priv->tx_irq[j], &priv->dma_conf.tx_queue[j]);
3570 irq_idx = priv->plat->rx_queues_to_use;
3572 case REQ_IRQ_ERR_RX:
3573 for (j = irq_idx - 1; j >= 0; j--) {
3574 if (priv->rx_irq[j] > 0) {
3575 irq_set_affinity_hint(priv->rx_irq[j], NULL);
3576 free_irq(priv->rx_irq[j], &priv->dma_conf.rx_queue[j]);
3580 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq)
3581 free_irq(priv->sfty_ue_irq, dev);
3583 case REQ_IRQ_ERR_SFTY_UE:
3584 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq)
3585 free_irq(priv->sfty_ce_irq, dev);
3587 case REQ_IRQ_ERR_SFTY_CE:
3588 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq)
3589 free_irq(priv->lpi_irq, dev);
3591 case REQ_IRQ_ERR_LPI:
3592 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq)
3593 free_irq(priv->wol_irq, dev);
3595 case REQ_IRQ_ERR_WOL:
3596 free_irq(dev->irq, dev);
3598 case REQ_IRQ_ERR_MAC:
3599 case REQ_IRQ_ERR_NO:
3600 /* If MAC IRQ request error, no more IRQ to free */
3605 static int stmmac_request_irq_multi_msi(struct net_device *dev)
3607 struct stmmac_priv *priv = netdev_priv(dev);
3608 enum request_irq_err irq_err;
3615 /* For common interrupt */
3616 int_name = priv->int_name_mac;
3617 sprintf(int_name, "%s:%s", dev->name, "mac");
3618 ret = request_irq(dev->irq, stmmac_mac_interrupt,
3620 if (unlikely(ret < 0)) {
3621 netdev_err(priv->dev,
3622 "%s: alloc mac MSI %d (error: %d)\n",
3623 __func__, dev->irq, ret);
3624 irq_err = REQ_IRQ_ERR_MAC;
3628 /* Request the Wake IRQ in case of another line
3631 priv->wol_irq_disabled = true;
3632 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) {
3633 int_name = priv->int_name_wol;
3634 sprintf(int_name, "%s:%s", dev->name, "wol");
3635 ret = request_irq(priv->wol_irq,
3636 stmmac_mac_interrupt,
3638 if (unlikely(ret < 0)) {
3639 netdev_err(priv->dev,
3640 "%s: alloc wol MSI %d (error: %d)\n",
3641 __func__, priv->wol_irq, ret);
3642 irq_err = REQ_IRQ_ERR_WOL;
3647 /* Request the LPI IRQ in case of another line
3650 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) {
3651 int_name = priv->int_name_lpi;
3652 sprintf(int_name, "%s:%s", dev->name, "lpi");
3653 ret = request_irq(priv->lpi_irq,
3654 stmmac_mac_interrupt,
3656 if (unlikely(ret < 0)) {
3657 netdev_err(priv->dev,
3658 "%s: alloc lpi MSI %d (error: %d)\n",
3659 __func__, priv->lpi_irq, ret);
3660 irq_err = REQ_IRQ_ERR_LPI;
3665 /* Request the Safety Feature Correctible Error line in
3666 * case of another line is used
3668 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) {
3669 int_name = priv->int_name_sfty_ce;
3670 sprintf(int_name, "%s:%s", dev->name, "safety-ce");
3671 ret = request_irq(priv->sfty_ce_irq,
3672 stmmac_safety_interrupt,
3674 if (unlikely(ret < 0)) {
3675 netdev_err(priv->dev,
3676 "%s: alloc sfty ce MSI %d (error: %d)\n",
3677 __func__, priv->sfty_ce_irq, ret);
3678 irq_err = REQ_IRQ_ERR_SFTY_CE;
3683 /* Request the Safety Feature Uncorrectible Error line in
3684 * case of another line is used
3686 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) {
3687 int_name = priv->int_name_sfty_ue;
3688 sprintf(int_name, "%s:%s", dev->name, "safety-ue");
3689 ret = request_irq(priv->sfty_ue_irq,
3690 stmmac_safety_interrupt,
3692 if (unlikely(ret < 0)) {
3693 netdev_err(priv->dev,
3694 "%s: alloc sfty ue MSI %d (error: %d)\n",
3695 __func__, priv->sfty_ue_irq, ret);
3696 irq_err = REQ_IRQ_ERR_SFTY_UE;
3701 /* Request Rx MSI irq */
3702 for (i = 0; i < priv->plat->rx_queues_to_use; i++) {
3703 if (i >= MTL_MAX_RX_QUEUES)
3705 if (priv->rx_irq[i] == 0)
3708 int_name = priv->int_name_rx_irq[i];
3709 sprintf(int_name, "%s:%s-%d", dev->name, "rx", i);
3710 ret = request_irq(priv->rx_irq[i],
3712 0, int_name, &priv->dma_conf.rx_queue[i]);
3713 if (unlikely(ret < 0)) {
3714 netdev_err(priv->dev,
3715 "%s: alloc rx-%d MSI %d (error: %d)\n",
3716 __func__, i, priv->rx_irq[i], ret);
3717 irq_err = REQ_IRQ_ERR_RX;
3721 cpumask_clear(&cpu_mask);
3722 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask);
3723 irq_set_affinity_hint(priv->rx_irq[i], &cpu_mask);
3726 /* Request Tx MSI irq */
3727 for (i = 0; i < priv->plat->tx_queues_to_use; i++) {
3728 if (i >= MTL_MAX_TX_QUEUES)
3730 if (priv->tx_irq[i] == 0)
3733 int_name = priv->int_name_tx_irq[i];
3734 sprintf(int_name, "%s:%s-%d", dev->name, "tx", i);
3735 ret = request_irq(priv->tx_irq[i],
3737 0, int_name, &priv->dma_conf.tx_queue[i]);
3738 if (unlikely(ret < 0)) {
3739 netdev_err(priv->dev,
3740 "%s: alloc tx-%d MSI %d (error: %d)\n",
3741 __func__, i, priv->tx_irq[i], ret);
3742 irq_err = REQ_IRQ_ERR_TX;
3746 cpumask_clear(&cpu_mask);
3747 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask);
3748 irq_set_affinity_hint(priv->tx_irq[i], &cpu_mask);
3754 stmmac_free_irq(dev, irq_err, irq_idx);
3758 static int stmmac_request_irq_single(struct net_device *dev)
3760 struct stmmac_priv *priv = netdev_priv(dev);
3761 enum request_irq_err irq_err;
3764 ret = request_irq(dev->irq, stmmac_interrupt,
3765 IRQF_SHARED, dev->name, dev);
3766 if (unlikely(ret < 0)) {
3767 netdev_err(priv->dev,
3768 "%s: ERROR: allocating the IRQ %d (error: %d)\n",
3769 __func__, dev->irq, ret);
3770 irq_err = REQ_IRQ_ERR_MAC;
3774 /* Request the Wake IRQ in case of another line
3777 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) {
3778 ret = request_irq(priv->wol_irq, stmmac_interrupt,
3779 IRQF_SHARED, dev->name, dev);
3780 if (unlikely(ret < 0)) {
3781 netdev_err(priv->dev,
3782 "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
3783 __func__, priv->wol_irq, ret);
3784 irq_err = REQ_IRQ_ERR_WOL;
3789 /* Request the IRQ lines */
3790 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) {
3791 ret = request_irq(priv->lpi_irq, stmmac_interrupt,
3792 IRQF_SHARED, dev->name, dev);
3793 if (unlikely(ret < 0)) {
3794 netdev_err(priv->dev,
3795 "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
3796 __func__, priv->lpi_irq, ret);
3797 irq_err = REQ_IRQ_ERR_LPI;
3805 stmmac_free_irq(dev, irq_err, 0);
3809 static int stmmac_request_irq(struct net_device *dev)
3811 struct stmmac_priv *priv = netdev_priv(dev);
3814 /* Request the IRQ lines */
3815 if (priv->plat->flags & STMMAC_FLAG_MULTI_MSI_EN)
3816 ret = stmmac_request_irq_multi_msi(dev);
3818 ret = stmmac_request_irq_single(dev);
3824 * stmmac_setup_dma_desc - Generate a dma_conf and allocate DMA queue
3825 * @priv: driver private structure
3826 * @mtu: MTU to setup the dma queue and buf with
3827 * Description: Allocate and generate a dma_conf based on the provided MTU.
3828 * Allocate the Tx/Rx DMA queue and init them.
3830 * the dma_conf allocated struct on success and an appropriate ERR_PTR on failure.
3832 static struct stmmac_dma_conf *
3833 stmmac_setup_dma_desc(struct stmmac_priv *priv, unsigned int mtu)
3835 struct stmmac_dma_conf *dma_conf;
3836 int chan, bfsize, ret;
3838 dma_conf = kzalloc(sizeof(*dma_conf), GFP_KERNEL);
3840 netdev_err(priv->dev, "%s: DMA conf allocation failed\n",
3842 return ERR_PTR(-ENOMEM);
3845 bfsize = stmmac_set_16kib_bfsize(priv, mtu);
3849 if (bfsize < BUF_SIZE_16KiB)
3850 bfsize = stmmac_set_bfsize(mtu, 0);
3852 dma_conf->dma_buf_sz = bfsize;
3853 /* Chose the tx/rx size from the already defined one in the
3854 * priv struct. (if defined)
3856 dma_conf->dma_tx_size = priv->dma_conf.dma_tx_size;
3857 dma_conf->dma_rx_size = priv->dma_conf.dma_rx_size;
3859 if (!dma_conf->dma_tx_size)
3860 dma_conf->dma_tx_size = DMA_DEFAULT_TX_SIZE;
3861 if (!dma_conf->dma_rx_size)
3862 dma_conf->dma_rx_size = DMA_DEFAULT_RX_SIZE;
3864 /* Earlier check for TBS */
3865 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) {
3866 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[chan];
3867 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en;
3869 /* Setup per-TXQ tbs flag before TX descriptor alloc */
3870 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0;
3873 ret = alloc_dma_desc_resources(priv, dma_conf);
3875 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
3880 ret = init_dma_desc_rings(priv->dev, dma_conf, GFP_KERNEL);
3882 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
3890 free_dma_desc_resources(priv, dma_conf);
3893 return ERR_PTR(ret);
3897 * __stmmac_open - open entry point of the driver
3898 * @dev : pointer to the device structure.
3899 * @dma_conf : structure to take the dma data
3901 * This function is the open entry point of the driver.
3903 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3906 static int __stmmac_open(struct net_device *dev,
3907 struct stmmac_dma_conf *dma_conf)
3909 struct stmmac_priv *priv = netdev_priv(dev);
3910 int mode = priv->plat->phy_interface;
3914 ret = pm_runtime_resume_and_get(priv->device);
3918 if (priv->hw->pcs != STMMAC_PCS_TBI &&
3919 priv->hw->pcs != STMMAC_PCS_RTBI &&
3921 xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73) &&
3922 !priv->hw->lynx_pcs) {
3923 ret = stmmac_init_phy(dev);
3925 netdev_err(priv->dev,
3926 "%s: Cannot attach to PHY (error: %d)\n",
3928 goto init_phy_error;
3932 priv->rx_copybreak = STMMAC_RX_COPYBREAK;
3934 buf_sz = dma_conf->dma_buf_sz;
3935 memcpy(&priv->dma_conf, dma_conf, sizeof(*dma_conf));
3937 stmmac_reset_queues_param(priv);
3939 if (!(priv->plat->flags & STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP) &&
3940 priv->plat->serdes_powerup) {
3941 ret = priv->plat->serdes_powerup(dev, priv->plat->bsp_priv);
3943 netdev_err(priv->dev, "%s: Serdes powerup failed\n",
3949 ret = stmmac_hw_setup(dev, true);
3951 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
3955 stmmac_init_coalesce(priv);
3957 phylink_start(priv->phylink);
3958 /* We may have called phylink_speed_down before */
3959 phylink_speed_up(priv->phylink);
3961 ret = stmmac_request_irq(dev);
3965 stmmac_enable_all_queues(priv);
3966 netif_tx_start_all_queues(priv->dev);
3967 stmmac_enable_all_dma_irq(priv);
3972 phylink_stop(priv->phylink);
3974 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
3975 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer);
3977 stmmac_hw_teardown(dev);
3979 phylink_disconnect_phy(priv->phylink);
3981 pm_runtime_put(priv->device);
3985 static int stmmac_open(struct net_device *dev)
3987 struct stmmac_priv *priv = netdev_priv(dev);
3988 struct stmmac_dma_conf *dma_conf;
3991 dma_conf = stmmac_setup_dma_desc(priv, dev->mtu);
3992 if (IS_ERR(dma_conf))
3993 return PTR_ERR(dma_conf);
3995 ret = __stmmac_open(dev, dma_conf);
3997 free_dma_desc_resources(priv, dma_conf);
4003 static void stmmac_fpe_stop_wq(struct stmmac_priv *priv)
4005 set_bit(__FPE_REMOVING, &priv->fpe_task_state);
4008 destroy_workqueue(priv->fpe_wq);
4010 netdev_info(priv->dev, "FPE workqueue stop");
4014 * stmmac_release - close entry point of the driver
4015 * @dev : device pointer.
4017 * This is the stop entry point of the driver.
4019 static int stmmac_release(struct net_device *dev)
4021 struct stmmac_priv *priv = netdev_priv(dev);
4024 if (device_may_wakeup(priv->device))
4025 phylink_speed_down(priv->phylink, false);
4026 /* Stop and disconnect the PHY */
4027 phylink_stop(priv->phylink);
4028 phylink_disconnect_phy(priv->phylink);
4030 stmmac_disable_all_queues(priv);
4032 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
4033 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer);
4035 netif_tx_disable(dev);
4037 /* Free the IRQ lines */
4038 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0);
4040 if (priv->eee_enabled) {
4041 priv->tx_path_in_lpi_mode = false;
4042 del_timer_sync(&priv->eee_ctrl_timer);
4045 /* Stop TX/RX DMA and clear the descriptors */
4046 stmmac_stop_all_dma(priv);
4048 /* Release and free the Rx/Tx resources */
4049 free_dma_desc_resources(priv, &priv->dma_conf);
4051 /* Disable the MAC Rx/Tx */
4052 stmmac_mac_set(priv, priv->ioaddr, false);
4054 /* Powerdown Serdes if there is */
4055 if (priv->plat->serdes_powerdown)
4056 priv->plat->serdes_powerdown(dev, priv->plat->bsp_priv);
4058 netif_carrier_off(dev);
4060 stmmac_release_ptp(priv);
4062 pm_runtime_put(priv->device);
4064 if (priv->dma_cap.fpesel)
4065 stmmac_fpe_stop_wq(priv);
4070 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb,
4071 struct stmmac_tx_queue *tx_q)
4073 u16 tag = 0x0, inner_tag = 0x0;
4074 u32 inner_type = 0x0;
4077 if (!priv->dma_cap.vlins)
4079 if (!skb_vlan_tag_present(skb))
4081 if (skb->vlan_proto == htons(ETH_P_8021AD)) {
4082 inner_tag = skb_vlan_tag_get(skb);
4083 inner_type = STMMAC_VLAN_INSERT;
4086 tag = skb_vlan_tag_get(skb);
4088 if (tx_q->tbs & STMMAC_TBS_AVAIL)
4089 p = &tx_q->dma_entx[tx_q->cur_tx].basic;
4091 p = &tx_q->dma_tx[tx_q->cur_tx];
4093 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type))
4096 stmmac_set_tx_owner(priv, p);
4097 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size);
4102 * stmmac_tso_allocator - close entry point of the driver
4103 * @priv: driver private structure
4104 * @des: buffer start address
4105 * @total_len: total length to fill in descriptors
4106 * @last_segment: condition for the last descriptor
4107 * @queue: TX queue index
4109 * This function fills descriptor and request new descriptors according to
4110 * buffer length to fill
4112 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des,
4113 int total_len, bool last_segment, u32 queue)
4115 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
4116 struct dma_desc *desc;
4120 tmp_len = total_len;
4122 while (tmp_len > 0) {
4123 dma_addr_t curr_addr;
4125 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx,
4126 priv->dma_conf.dma_tx_size);
4127 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
4129 if (tx_q->tbs & STMMAC_TBS_AVAIL)
4130 desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
4132 desc = &tx_q->dma_tx[tx_q->cur_tx];
4134 curr_addr = des + (total_len - tmp_len);
4135 if (priv->dma_cap.addr64 <= 32)
4136 desc->des0 = cpu_to_le32(curr_addr);
4138 stmmac_set_desc_addr(priv, desc, curr_addr);
4140 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
4141 TSO_MAX_BUFF_SIZE : tmp_len;
4143 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size,
4145 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
4148 tmp_len -= TSO_MAX_BUFF_SIZE;
4152 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue)
4154 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
4157 if (likely(priv->extend_desc))
4158 desc_size = sizeof(struct dma_extended_desc);
4159 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4160 desc_size = sizeof(struct dma_edesc);
4162 desc_size = sizeof(struct dma_desc);
4164 /* The own bit must be the latest setting done when prepare the
4165 * descriptor and then barrier is needed to make sure that
4166 * all is coherent before granting the DMA engine.
4170 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size);
4171 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
4175 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
4176 * @skb : the socket buffer
4177 * @dev : device pointer
4178 * Description: this is the transmit function that is called on TSO frames
4179 * (support available on GMAC4 and newer chips).
4180 * Diagram below show the ring programming in case of TSO frames:
4184 * | DES0 |---> buffer1 = L2/L3/L4 header
4185 * | DES1 |---> TCP Payload (can continue on next descr...)
4186 * | DES2 |---> buffer 1 and 2 len
4187 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
4193 * | DES0 | --| Split TCP Payload on Buffers 1 and 2
4195 * | DES2 | --> buffer 1 and 2 len
4199 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
4201 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
4203 struct dma_desc *desc, *first, *mss_desc = NULL;
4204 struct stmmac_priv *priv = netdev_priv(dev);
4205 int nfrags = skb_shinfo(skb)->nr_frags;
4206 u32 queue = skb_get_queue_mapping(skb);
4207 unsigned int first_entry, tx_packets;
4208 struct stmmac_txq_stats *txq_stats;
4209 int tmp_pay_len = 0, first_tx;
4210 struct stmmac_tx_queue *tx_q;
4211 bool has_vlan, set_ic;
4212 u8 proto_hdr_len, hdr;
4213 unsigned long flags;
4218 tx_q = &priv->dma_conf.tx_queue[queue];
4219 txq_stats = &priv->xstats.txq_stats[queue];
4220 first_tx = tx_q->cur_tx;
4222 /* Compute header lengths */
4223 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
4224 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr);
4225 hdr = sizeof(struct udphdr);
4227 proto_hdr_len = skb_tcp_all_headers(skb);
4228 hdr = tcp_hdrlen(skb);
4231 /* Desc availability based on threshold should be enough safe */
4232 if (unlikely(stmmac_tx_avail(priv, queue) <
4233 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
4234 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
4235 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
4237 /* This is a hard error, log it. */
4238 netdev_err(priv->dev,
4239 "%s: Tx Ring full when queue awake\n",
4242 return NETDEV_TX_BUSY;
4245 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
4247 mss = skb_shinfo(skb)->gso_size;
4249 /* set new MSS value if needed */
4250 if (mss != tx_q->mss) {
4251 if (tx_q->tbs & STMMAC_TBS_AVAIL)
4252 mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
4254 mss_desc = &tx_q->dma_tx[tx_q->cur_tx];
4256 stmmac_set_mss(priv, mss_desc, mss);
4258 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx,
4259 priv->dma_conf.dma_tx_size);
4260 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
4263 if (netif_msg_tx_queued(priv)) {
4264 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
4265 __func__, hdr, proto_hdr_len, pay_len, mss);
4266 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
4270 /* Check if VLAN can be inserted by HW */
4271 has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
4273 first_entry = tx_q->cur_tx;
4274 WARN_ON(tx_q->tx_skbuff[first_entry]);
4276 if (tx_q->tbs & STMMAC_TBS_AVAIL)
4277 desc = &tx_q->dma_entx[first_entry].basic;
4279 desc = &tx_q->dma_tx[first_entry];
4283 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
4285 /* first descriptor: fill Headers on Buf1 */
4286 des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
4288 if (dma_mapping_error(priv->device, des))
4291 tx_q->tx_skbuff_dma[first_entry].buf = des;
4292 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
4293 tx_q->tx_skbuff_dma[first_entry].map_as_page = false;
4294 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB;
4296 if (priv->dma_cap.addr64 <= 32) {
4297 first->des0 = cpu_to_le32(des);
4299 /* Fill start of payload in buff2 of first descriptor */
4301 first->des1 = cpu_to_le32(des + proto_hdr_len);
4303 /* If needed take extra descriptors to fill the remaining payload */
4304 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
4306 stmmac_set_desc_addr(priv, first, des);
4307 tmp_pay_len = pay_len;
4308 des += proto_hdr_len;
4312 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
4314 /* Prepare fragments */
4315 for (i = 0; i < nfrags; i++) {
4316 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4318 des = skb_frag_dma_map(priv->device, frag, 0,
4319 skb_frag_size(frag),
4321 if (dma_mapping_error(priv->device, des))
4324 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
4325 (i == nfrags - 1), queue);
4327 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
4328 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
4329 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
4330 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB;
4333 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
4335 /* Only the last descriptor gets to point to the skb. */
4336 tx_q->tx_skbuff[tx_q->cur_tx] = skb;
4337 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB;
4339 /* Manage tx mitigation */
4340 tx_packets = (tx_q->cur_tx + 1) - first_tx;
4341 tx_q->tx_count_frames += tx_packets;
4343 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en)
4345 else if (!priv->tx_coal_frames[queue])
4347 else if (tx_packets > priv->tx_coal_frames[queue])
4349 else if ((tx_q->tx_count_frames %
4350 priv->tx_coal_frames[queue]) < tx_packets)
4356 if (tx_q->tbs & STMMAC_TBS_AVAIL)
4357 desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
4359 desc = &tx_q->dma_tx[tx_q->cur_tx];
4361 tx_q->tx_count_frames = 0;
4362 stmmac_set_tx_ic(priv, desc);
4365 /* We've used all descriptors we need for this skb, however,
4366 * advance cur_tx so that it references a fresh descriptor.
4367 * ndo_start_xmit will fill this descriptor the next time it's
4368 * called and stmmac_tx_clean may clean up to this descriptor.
4370 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size);
4372 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
4373 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
4375 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
4378 flags = u64_stats_update_begin_irqsave(&txq_stats->syncp);
4379 txq_stats->tx_bytes += skb->len;
4380 txq_stats->tx_tso_frames++;
4381 txq_stats->tx_tso_nfrags += nfrags;
4383 txq_stats->tx_set_ic_bit++;
4384 u64_stats_update_end_irqrestore(&txq_stats->syncp, flags);
4386 if (priv->sarc_type)
4387 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
4389 skb_tx_timestamp(skb);
4391 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4392 priv->hwts_tx_en)) {
4393 /* declare that device is doing timestamping */
4394 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4395 stmmac_enable_tx_timestamp(priv, first);
4398 /* Complete the first descriptor before granting the DMA */
4399 stmmac_prepare_tso_tx_desc(priv, first, 1,
4402 1, tx_q->tx_skbuff_dma[first_entry].last_segment,
4403 hdr / 4, (skb->len - proto_hdr_len));
4405 /* If context desc is used to change MSS */
4407 /* Make sure that first descriptor has been completely
4408 * written, including its own bit. This is because MSS is
4409 * actually before first descriptor, so we need to make
4410 * sure that MSS's own bit is the last thing written.
4413 stmmac_set_tx_owner(priv, mss_desc);
4416 if (netif_msg_pktdata(priv)) {
4417 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
4418 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
4419 tx_q->cur_tx, first, nfrags);
4420 pr_info(">>> frame to be transmitted: ");
4421 print_pkt(skb->data, skb_headlen(skb));
4424 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
4426 stmmac_flush_tx_descriptors(priv, queue);
4427 stmmac_tx_timer_arm(priv, queue);
4429 return NETDEV_TX_OK;
4432 dev_err(priv->device, "Tx dma map failed\n");
4434 priv->xstats.tx_dropped++;
4435 return NETDEV_TX_OK;
4439 * stmmac_has_ip_ethertype() - Check if packet has IP ethertype
4440 * @skb: socket buffer to check
4442 * Check if a packet has an ethertype that will trigger the IP header checks
4443 * and IP/TCP checksum engine of the stmmac core.
4445 * Return: true if the ethertype can trigger the checksum engine, false
4448 static bool stmmac_has_ip_ethertype(struct sk_buff *skb)
4453 proto = __vlan_get_protocol(skb, eth_header_parse_protocol(skb),
4456 return (depth <= ETH_HLEN) &&
4457 (proto == htons(ETH_P_IP) || proto == htons(ETH_P_IPV6));
4461 * stmmac_xmit - Tx entry point of the driver
4462 * @skb : the socket buffer
4463 * @dev : device pointer
4464 * Description : this is the tx entry point of the driver.
4465 * It programs the chain or the ring and supports oversized frames
4468 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
4470 unsigned int first_entry, tx_packets, enh_desc;
4471 struct stmmac_priv *priv = netdev_priv(dev);
4472 unsigned int nopaged_len = skb_headlen(skb);
4473 int i, csum_insertion = 0, is_jumbo = 0;
4474 u32 queue = skb_get_queue_mapping(skb);
4475 int nfrags = skb_shinfo(skb)->nr_frags;
4476 int gso = skb_shinfo(skb)->gso_type;
4477 struct stmmac_txq_stats *txq_stats;
4478 struct dma_edesc *tbs_desc = NULL;
4479 struct dma_desc *desc, *first;
4480 struct stmmac_tx_queue *tx_q;
4481 bool has_vlan, set_ic;
4482 int entry, first_tx;
4483 unsigned long flags;
4486 tx_q = &priv->dma_conf.tx_queue[queue];
4487 txq_stats = &priv->xstats.txq_stats[queue];
4488 first_tx = tx_q->cur_tx;
4490 if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en)
4491 stmmac_disable_eee_mode(priv);
4493 /* Manage oversized TCP frames for GMAC4 device */
4494 if (skb_is_gso(skb) && priv->tso) {
4495 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6))
4496 return stmmac_tso_xmit(skb, dev);
4497 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4))
4498 return stmmac_tso_xmit(skb, dev);
4501 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
4502 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
4503 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
4505 /* This is a hard error, log it. */
4506 netdev_err(priv->dev,
4507 "%s: Tx Ring full when queue awake\n",
4510 return NETDEV_TX_BUSY;
4513 /* Check if VLAN can be inserted by HW */
4514 has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
4516 entry = tx_q->cur_tx;
4517 first_entry = entry;
4518 WARN_ON(tx_q->tx_skbuff[first_entry]);
4520 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
4521 /* DWMAC IPs can be synthesized to support tx coe only for a few tx
4522 * queues. In that case, checksum offloading for those queues that don't
4523 * support tx coe needs to fallback to software checksum calculation.
4525 * Packets that won't trigger the COE e.g. most DSA-tagged packets will
4526 * also have to be checksummed in software.
4528 if (csum_insertion &&
4529 (priv->plat->tx_queues_cfg[queue].coe_unsupported ||
4530 !stmmac_has_ip_ethertype(skb))) {
4531 if (unlikely(skb_checksum_help(skb)))
4533 csum_insertion = !csum_insertion;
4536 if (likely(priv->extend_desc))
4537 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4538 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4539 desc = &tx_q->dma_entx[entry].basic;
4541 desc = tx_q->dma_tx + entry;
4546 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
4548 enh_desc = priv->plat->enh_desc;
4549 /* To program the descriptors according to the size of the frame */
4551 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc);
4553 if (unlikely(is_jumbo)) {
4554 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion);
4555 if (unlikely(entry < 0) && (entry != -EINVAL))
4559 for (i = 0; i < nfrags; i++) {
4560 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4561 int len = skb_frag_size(frag);
4562 bool last_segment = (i == (nfrags - 1));
4564 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size);
4565 WARN_ON(tx_q->tx_skbuff[entry]);
4567 if (likely(priv->extend_desc))
4568 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4569 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4570 desc = &tx_q->dma_entx[entry].basic;
4572 desc = tx_q->dma_tx + entry;
4574 des = skb_frag_dma_map(priv->device, frag, 0, len,
4576 if (dma_mapping_error(priv->device, des))
4577 goto dma_map_err; /* should reuse desc w/o issues */
4579 tx_q->tx_skbuff_dma[entry].buf = des;
4581 stmmac_set_desc_addr(priv, desc, des);
4583 tx_q->tx_skbuff_dma[entry].map_as_page = true;
4584 tx_q->tx_skbuff_dma[entry].len = len;
4585 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
4586 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB;
4588 /* Prepare the descriptor and set the own bit too */
4589 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion,
4590 priv->mode, 1, last_segment, skb->len);
4593 /* Only the last descriptor gets to point to the skb. */
4594 tx_q->tx_skbuff[entry] = skb;
4595 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB;
4597 /* According to the coalesce parameter the IC bit for the latest
4598 * segment is reset and the timer re-started to clean the tx status.
4599 * This approach takes care about the fragments: desc is the first
4600 * element in case of no SG.
4602 tx_packets = (entry + 1) - first_tx;
4603 tx_q->tx_count_frames += tx_packets;
4605 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en)
4607 else if (!priv->tx_coal_frames[queue])
4609 else if (tx_packets > priv->tx_coal_frames[queue])
4611 else if ((tx_q->tx_count_frames %
4612 priv->tx_coal_frames[queue]) < tx_packets)
4618 if (likely(priv->extend_desc))
4619 desc = &tx_q->dma_etx[entry].basic;
4620 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4621 desc = &tx_q->dma_entx[entry].basic;
4623 desc = &tx_q->dma_tx[entry];
4625 tx_q->tx_count_frames = 0;
4626 stmmac_set_tx_ic(priv, desc);
4629 /* We've used all descriptors we need for this skb, however,
4630 * advance cur_tx so that it references a fresh descriptor.
4631 * ndo_start_xmit will fill this descriptor the next time it's
4632 * called and stmmac_tx_clean may clean up to this descriptor.
4634 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size);
4635 tx_q->cur_tx = entry;
4637 if (netif_msg_pktdata(priv)) {
4638 netdev_dbg(priv->dev,
4639 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
4640 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
4641 entry, first, nfrags);
4643 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
4644 print_pkt(skb->data, skb->len);
4647 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
4648 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
4650 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
4653 flags = u64_stats_update_begin_irqsave(&txq_stats->syncp);
4654 txq_stats->tx_bytes += skb->len;
4656 txq_stats->tx_set_ic_bit++;
4657 u64_stats_update_end_irqrestore(&txq_stats->syncp, flags);
4659 if (priv->sarc_type)
4660 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
4662 skb_tx_timestamp(skb);
4664 /* Ready to fill the first descriptor and set the OWN bit w/o any
4665 * problems because all the descriptors are actually ready to be
4666 * passed to the DMA engine.
4668 if (likely(!is_jumbo)) {
4669 bool last_segment = (nfrags == 0);
4671 des = dma_map_single(priv->device, skb->data,
4672 nopaged_len, DMA_TO_DEVICE);
4673 if (dma_mapping_error(priv->device, des))
4676 tx_q->tx_skbuff_dma[first_entry].buf = des;
4677 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB;
4678 tx_q->tx_skbuff_dma[first_entry].map_as_page = false;
4680 stmmac_set_desc_addr(priv, first, des);
4682 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
4683 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
4685 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4686 priv->hwts_tx_en)) {
4687 /* declare that device is doing timestamping */
4688 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4689 stmmac_enable_tx_timestamp(priv, first);
4692 /* Prepare the first descriptor setting the OWN bit too */
4693 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
4694 csum_insertion, priv->mode, 0, last_segment,
4698 if (tx_q->tbs & STMMAC_TBS_EN) {
4699 struct timespec64 ts = ns_to_timespec64(skb->tstamp);
4701 tbs_desc = &tx_q->dma_entx[first_entry];
4702 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec);
4705 stmmac_set_tx_owner(priv, first);
4707 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
4709 stmmac_enable_dma_transmission(priv, priv->ioaddr);
4711 stmmac_flush_tx_descriptors(priv, queue);
4712 stmmac_tx_timer_arm(priv, queue);
4714 return NETDEV_TX_OK;
4717 netdev_err(priv->dev, "Tx DMA map failed\n");
4719 priv->xstats.tx_dropped++;
4720 return NETDEV_TX_OK;
4723 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
4725 struct vlan_ethhdr *veth = skb_vlan_eth_hdr(skb);
4726 __be16 vlan_proto = veth->h_vlan_proto;
4729 if ((vlan_proto == htons(ETH_P_8021Q) &&
4730 dev->features & NETIF_F_HW_VLAN_CTAG_RX) ||
4731 (vlan_proto == htons(ETH_P_8021AD) &&
4732 dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
4733 /* pop the vlan tag */
4734 vlanid = ntohs(veth->h_vlan_TCI);
4735 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2);
4736 skb_pull(skb, VLAN_HLEN);
4737 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid);
4742 * stmmac_rx_refill - refill used skb preallocated buffers
4743 * @priv: driver private structure
4744 * @queue: RX queue index
4745 * Description : this is to reallocate the skb for the reception process
4746 * that is based on zero-copy.
4748 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
4750 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
4751 int dirty = stmmac_rx_dirty(priv, queue);
4752 unsigned int entry = rx_q->dirty_rx;
4753 gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN);
4755 if (priv->dma_cap.host_dma_width <= 32)
4758 while (dirty-- > 0) {
4759 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
4763 if (priv->extend_desc)
4764 p = (struct dma_desc *)(rx_q->dma_erx + entry);
4766 p = rx_q->dma_rx + entry;
4769 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp);
4774 if (priv->sph && !buf->sec_page) {
4775 buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp);
4779 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
4782 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset;
4784 stmmac_set_desc_addr(priv, p, buf->addr);
4786 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true);
4788 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false);
4789 stmmac_refill_desc3(priv, rx_q, p);
4791 rx_q->rx_count_frames++;
4792 rx_q->rx_count_frames += priv->rx_coal_frames[queue];
4793 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue])
4794 rx_q->rx_count_frames = 0;
4796 use_rx_wd = !priv->rx_coal_frames[queue];
4797 use_rx_wd |= rx_q->rx_count_frames > 0;
4798 if (!priv->use_riwt)
4802 stmmac_set_rx_owner(priv, p, use_rx_wd);
4804 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_rx_size);
4806 rx_q->dirty_rx = entry;
4807 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
4808 (rx_q->dirty_rx * sizeof(struct dma_desc));
4809 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
4812 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv,
4814 int status, unsigned int len)
4816 unsigned int plen = 0, hlen = 0;
4817 int coe = priv->hw->rx_csum;
4819 /* Not first descriptor, buffer is always zero */
4820 if (priv->sph && len)
4823 /* First descriptor, get split header length */
4824 stmmac_get_rx_header_len(priv, p, &hlen);
4825 if (priv->sph && hlen) {
4826 priv->xstats.rx_split_hdr_pkt_n++;
4830 /* First descriptor, not last descriptor and not split header */
4831 if (status & rx_not_ls)
4832 return priv->dma_conf.dma_buf_sz;
4834 plen = stmmac_get_rx_frame_len(priv, p, coe);
4836 /* First descriptor and last descriptor and not split header */
4837 return min_t(unsigned int, priv->dma_conf.dma_buf_sz, plen);
4840 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv,
4842 int status, unsigned int len)
4844 int coe = priv->hw->rx_csum;
4845 unsigned int plen = 0;
4847 /* Not split header, buffer is not available */
4851 /* Not last descriptor */
4852 if (status & rx_not_ls)
4853 return priv->dma_conf.dma_buf_sz;
4855 plen = stmmac_get_rx_frame_len(priv, p, coe);
4857 /* Last descriptor */
4861 static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue,
4862 struct xdp_frame *xdpf, bool dma_map)
4864 struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[queue];
4865 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
4866 unsigned int entry = tx_q->cur_tx;
4867 struct dma_desc *tx_desc;
4868 dma_addr_t dma_addr;
4871 if (stmmac_tx_avail(priv, queue) < STMMAC_TX_THRESH(priv))
4872 return STMMAC_XDP_CONSUMED;
4874 if (likely(priv->extend_desc))
4875 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4876 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4877 tx_desc = &tx_q->dma_entx[entry].basic;
4879 tx_desc = tx_q->dma_tx + entry;
4882 dma_addr = dma_map_single(priv->device, xdpf->data,
4883 xdpf->len, DMA_TO_DEVICE);
4884 if (dma_mapping_error(priv->device, dma_addr))
4885 return STMMAC_XDP_CONSUMED;
4887 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_NDO;
4889 struct page *page = virt_to_page(xdpf->data);
4891 dma_addr = page_pool_get_dma_addr(page) + sizeof(*xdpf) +
4893 dma_sync_single_for_device(priv->device, dma_addr,
4894 xdpf->len, DMA_BIDIRECTIONAL);
4896 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_TX;
4899 tx_q->tx_skbuff_dma[entry].buf = dma_addr;
4900 tx_q->tx_skbuff_dma[entry].map_as_page = false;
4901 tx_q->tx_skbuff_dma[entry].len = xdpf->len;
4902 tx_q->tx_skbuff_dma[entry].last_segment = true;
4903 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
4905 tx_q->xdpf[entry] = xdpf;
4907 stmmac_set_desc_addr(priv, tx_desc, dma_addr);
4909 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len,
4910 true, priv->mode, true, true,
4913 tx_q->tx_count_frames++;
4915 if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0)
4921 unsigned long flags;
4922 tx_q->tx_count_frames = 0;
4923 stmmac_set_tx_ic(priv, tx_desc);
4924 flags = u64_stats_update_begin_irqsave(&txq_stats->syncp);
4925 txq_stats->tx_set_ic_bit++;
4926 u64_stats_update_end_irqrestore(&txq_stats->syncp, flags);
4929 stmmac_enable_dma_transmission(priv, priv->ioaddr);
4931 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size);
4932 tx_q->cur_tx = entry;
4934 return STMMAC_XDP_TX;
4937 static int stmmac_xdp_get_tx_queue(struct stmmac_priv *priv,
4942 if (unlikely(index < 0))
4945 while (index >= priv->plat->tx_queues_to_use)
4946 index -= priv->plat->tx_queues_to_use;
4951 static int stmmac_xdp_xmit_back(struct stmmac_priv *priv,
4952 struct xdp_buff *xdp)
4954 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
4955 int cpu = smp_processor_id();
4956 struct netdev_queue *nq;
4960 if (unlikely(!xdpf))
4961 return STMMAC_XDP_CONSUMED;
4963 queue = stmmac_xdp_get_tx_queue(priv, cpu);
4964 nq = netdev_get_tx_queue(priv->dev, queue);
4966 __netif_tx_lock(nq, cpu);
4967 /* Avoids TX time-out as we are sharing with slow path */
4968 txq_trans_cond_update(nq);
4970 res = stmmac_xdp_xmit_xdpf(priv, queue, xdpf, false);
4971 if (res == STMMAC_XDP_TX)
4972 stmmac_flush_tx_descriptors(priv, queue);
4974 __netif_tx_unlock(nq);
4979 static int __stmmac_xdp_run_prog(struct stmmac_priv *priv,
4980 struct bpf_prog *prog,
4981 struct xdp_buff *xdp)
4986 act = bpf_prog_run_xdp(prog, xdp);
4989 res = STMMAC_XDP_PASS;
4992 res = stmmac_xdp_xmit_back(priv, xdp);
4995 if (xdp_do_redirect(priv->dev, xdp, prog) < 0)
4996 res = STMMAC_XDP_CONSUMED;
4998 res = STMMAC_XDP_REDIRECT;
5001 bpf_warn_invalid_xdp_action(priv->dev, prog, act);
5004 trace_xdp_exception(priv->dev, prog, act);
5007 res = STMMAC_XDP_CONSUMED;
5014 static struct sk_buff *stmmac_xdp_run_prog(struct stmmac_priv *priv,
5015 struct xdp_buff *xdp)
5017 struct bpf_prog *prog;
5020 prog = READ_ONCE(priv->xdp_prog);
5022 res = STMMAC_XDP_PASS;
5026 res = __stmmac_xdp_run_prog(priv, prog, xdp);
5028 return ERR_PTR(-res);
5031 static void stmmac_finalize_xdp_rx(struct stmmac_priv *priv,
5034 int cpu = smp_processor_id();
5037 queue = stmmac_xdp_get_tx_queue(priv, cpu);
5039 if (xdp_status & STMMAC_XDP_TX)
5040 stmmac_tx_timer_arm(priv, queue);
5042 if (xdp_status & STMMAC_XDP_REDIRECT)
5046 static struct sk_buff *stmmac_construct_skb_zc(struct stmmac_channel *ch,
5047 struct xdp_buff *xdp)
5049 unsigned int metasize = xdp->data - xdp->data_meta;
5050 unsigned int datasize = xdp->data_end - xdp->data;
5051 struct sk_buff *skb;
5053 skb = __napi_alloc_skb(&ch->rxtx_napi,
5054 xdp->data_end - xdp->data_hard_start,
5055 GFP_ATOMIC | __GFP_NOWARN);
5059 skb_reserve(skb, xdp->data - xdp->data_hard_start);
5060 memcpy(__skb_put(skb, datasize), xdp->data, datasize);
5062 skb_metadata_set(skb, metasize);
5067 static void stmmac_dispatch_skb_zc(struct stmmac_priv *priv, u32 queue,
5068 struct dma_desc *p, struct dma_desc *np,
5069 struct xdp_buff *xdp)
5071 struct stmmac_rxq_stats *rxq_stats = &priv->xstats.rxq_stats[queue];
5072 struct stmmac_channel *ch = &priv->channel[queue];
5073 unsigned int len = xdp->data_end - xdp->data;
5074 enum pkt_hash_types hash_type;
5075 int coe = priv->hw->rx_csum;
5076 unsigned long flags;
5077 struct sk_buff *skb;
5080 skb = stmmac_construct_skb_zc(ch, xdp);
5082 priv->xstats.rx_dropped++;
5086 stmmac_get_rx_hwtstamp(priv, p, np, skb);
5087 if (priv->hw->hw_vlan_en)
5088 /* MAC level stripping. */
5089 stmmac_rx_hw_vlan(priv, priv->hw, p, skb);
5091 /* Driver level stripping. */
5092 stmmac_rx_vlan(priv->dev, skb);
5093 skb->protocol = eth_type_trans(skb, priv->dev);
5095 if (unlikely(!coe) || !stmmac_has_ip_ethertype(skb))
5096 skb_checksum_none_assert(skb);
5098 skb->ip_summed = CHECKSUM_UNNECESSARY;
5100 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type))
5101 skb_set_hash(skb, hash, hash_type);
5103 skb_record_rx_queue(skb, queue);
5104 napi_gro_receive(&ch->rxtx_napi, skb);
5106 flags = u64_stats_update_begin_irqsave(&rxq_stats->syncp);
5107 rxq_stats->rx_pkt_n++;
5108 rxq_stats->rx_bytes += len;
5109 u64_stats_update_end_irqrestore(&rxq_stats->syncp, flags);
5112 static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
5114 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
5115 unsigned int entry = rx_q->dirty_rx;
5116 struct dma_desc *rx_desc = NULL;
5119 budget = min(budget, stmmac_rx_dirty(priv, queue));
5121 while (budget-- > 0 && entry != rx_q->cur_rx) {
5122 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
5123 dma_addr_t dma_addr;
5127 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool);
5134 if (priv->extend_desc)
5135 rx_desc = (struct dma_desc *)(rx_q->dma_erx + entry);
5137 rx_desc = rx_q->dma_rx + entry;
5139 dma_addr = xsk_buff_xdp_get_dma(buf->xdp);
5140 stmmac_set_desc_addr(priv, rx_desc, dma_addr);
5141 stmmac_set_desc_sec_addr(priv, rx_desc, 0, false);
5142 stmmac_refill_desc3(priv, rx_q, rx_desc);
5144 rx_q->rx_count_frames++;
5145 rx_q->rx_count_frames += priv->rx_coal_frames[queue];
5146 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue])
5147 rx_q->rx_count_frames = 0;
5149 use_rx_wd = !priv->rx_coal_frames[queue];
5150 use_rx_wd |= rx_q->rx_count_frames > 0;
5151 if (!priv->use_riwt)
5155 stmmac_set_rx_owner(priv, rx_desc, use_rx_wd);
5157 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_rx_size);
5161 rx_q->dirty_rx = entry;
5162 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
5163 (rx_q->dirty_rx * sizeof(struct dma_desc));
5164 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
5170 static struct stmmac_xdp_buff *xsk_buff_to_stmmac_ctx(struct xdp_buff *xdp)
5172 /* In XDP zero copy data path, xdp field in struct xdp_buff_xsk is used
5173 * to represent incoming packet, whereas cb field in the same structure
5174 * is used to store driver specific info. Thus, struct stmmac_xdp_buff
5175 * is laid on top of xdp and cb fields of struct xdp_buff_xsk.
5177 return (struct stmmac_xdp_buff *)xdp;
5180 static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue)
5182 struct stmmac_rxq_stats *rxq_stats = &priv->xstats.rxq_stats[queue];
5183 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
5184 unsigned int count = 0, error = 0, len = 0;
5185 int dirty = stmmac_rx_dirty(priv, queue);
5186 unsigned int next_entry = rx_q->cur_rx;
5187 u32 rx_errors = 0, rx_dropped = 0;
5188 unsigned int desc_size;
5189 struct bpf_prog *prog;
5190 bool failure = false;
5191 unsigned long flags;
5195 if (netif_msg_rx_status(priv)) {
5198 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
5199 if (priv->extend_desc) {
5200 rx_head = (void *)rx_q->dma_erx;
5201 desc_size = sizeof(struct dma_extended_desc);
5203 rx_head = (void *)rx_q->dma_rx;
5204 desc_size = sizeof(struct dma_desc);
5207 stmmac_display_ring(priv, rx_head, priv->dma_conf.dma_rx_size, true,
5208 rx_q->dma_rx_phy, desc_size);
5210 while (count < limit) {
5211 struct stmmac_rx_buffer *buf;
5212 struct stmmac_xdp_buff *ctx;
5213 unsigned int buf1_len = 0;
5214 struct dma_desc *np, *p;
5218 if (!count && rx_q->state_saved) {
5219 error = rx_q->state.error;
5220 len = rx_q->state.len;
5222 rx_q->state_saved = false;
5233 buf = &rx_q->buf_pool[entry];
5235 if (dirty >= STMMAC_RX_FILL_BATCH) {
5236 failure = failure ||
5237 !stmmac_rx_refill_zc(priv, queue, dirty);
5241 if (priv->extend_desc)
5242 p = (struct dma_desc *)(rx_q->dma_erx + entry);
5244 p = rx_q->dma_rx + entry;
5246 /* read the status of the incoming frame */
5247 status = stmmac_rx_status(priv, &priv->xstats, p);
5248 /* check if managed by the DMA otherwise go ahead */
5249 if (unlikely(status & dma_own))
5252 /* Prefetch the next RX descriptor */
5253 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx,
5254 priv->dma_conf.dma_rx_size);
5255 next_entry = rx_q->cur_rx;
5257 if (priv->extend_desc)
5258 np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
5260 np = rx_q->dma_rx + next_entry;
5264 /* Ensure a valid XSK buffer before proceed */
5268 if (priv->extend_desc)
5269 stmmac_rx_extended_status(priv, &priv->xstats,
5270 rx_q->dma_erx + entry);
5271 if (unlikely(status == discard_frame)) {
5272 xsk_buff_free(buf->xdp);
5276 if (!priv->hwts_rx_en)
5280 if (unlikely(error && (status & rx_not_ls)))
5282 if (unlikely(error)) {
5287 /* XSK pool expects RX frame 1:1 mapped to XSK buffer */
5288 if (likely(status & rx_not_ls)) {
5289 xsk_buff_free(buf->xdp);
5296 ctx = xsk_buff_to_stmmac_ctx(buf->xdp);
5301 /* XDP ZC Frame only support primary buffers for now */
5302 buf1_len = stmmac_rx_buf1_len(priv, p, status, len);
5305 /* ACS is disabled; strip manually. */
5306 if (likely(!(status & rx_not_ls))) {
5307 buf1_len -= ETH_FCS_LEN;
5311 /* RX buffer is good and fit into a XSK pool buffer */
5312 buf->xdp->data_end = buf->xdp->data + buf1_len;
5313 xsk_buff_dma_sync_for_cpu(buf->xdp, rx_q->xsk_pool);
5315 prog = READ_ONCE(priv->xdp_prog);
5316 res = __stmmac_xdp_run_prog(priv, prog, buf->xdp);
5319 case STMMAC_XDP_PASS:
5320 stmmac_dispatch_skb_zc(priv, queue, p, np, buf->xdp);
5321 xsk_buff_free(buf->xdp);
5323 case STMMAC_XDP_CONSUMED:
5324 xsk_buff_free(buf->xdp);
5328 case STMMAC_XDP_REDIRECT:
5338 if (status & rx_not_ls) {
5339 rx_q->state_saved = true;
5340 rx_q->state.error = error;
5341 rx_q->state.len = len;
5344 stmmac_finalize_xdp_rx(priv, xdp_status);
5346 flags = u64_stats_update_begin_irqsave(&rxq_stats->syncp);
5347 rxq_stats->rx_pkt_n += count;
5348 u64_stats_update_end_irqrestore(&rxq_stats->syncp, flags);
5350 priv->xstats.rx_dropped += rx_dropped;
5351 priv->xstats.rx_errors += rx_errors;
5353 if (xsk_uses_need_wakeup(rx_q->xsk_pool)) {
5354 if (failure || stmmac_rx_dirty(priv, queue) > 0)
5355 xsk_set_rx_need_wakeup(rx_q->xsk_pool);
5357 xsk_clear_rx_need_wakeup(rx_q->xsk_pool);
5362 return failure ? limit : (int)count;
5366 * stmmac_rx - manage the receive process
5367 * @priv: driver private structure
5368 * @limit: napi bugget
5369 * @queue: RX queue index.
5370 * Description : this the function called by the napi poll method.
5371 * It gets all the frames inside the ring.
5373 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
5375 u32 rx_errors = 0, rx_dropped = 0, rx_bytes = 0, rx_packets = 0;
5376 struct stmmac_rxq_stats *rxq_stats = &priv->xstats.rxq_stats[queue];
5377 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
5378 struct stmmac_channel *ch = &priv->channel[queue];
5379 unsigned int count = 0, error = 0, len = 0;
5380 int status = 0, coe = priv->hw->rx_csum;
5381 unsigned int next_entry = rx_q->cur_rx;
5382 enum dma_data_direction dma_dir;
5383 unsigned int desc_size;
5384 struct sk_buff *skb = NULL;
5385 struct stmmac_xdp_buff ctx;
5386 unsigned long flags;
5390 dma_dir = page_pool_get_dma_dir(rx_q->page_pool);
5391 buf_sz = DIV_ROUND_UP(priv->dma_conf.dma_buf_sz, PAGE_SIZE) * PAGE_SIZE;
5392 limit = min(priv->dma_conf.dma_rx_size - 1, (unsigned int)limit);
5394 if (netif_msg_rx_status(priv)) {
5397 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
5398 if (priv->extend_desc) {
5399 rx_head = (void *)rx_q->dma_erx;
5400 desc_size = sizeof(struct dma_extended_desc);
5402 rx_head = (void *)rx_q->dma_rx;
5403 desc_size = sizeof(struct dma_desc);
5406 stmmac_display_ring(priv, rx_head, priv->dma_conf.dma_rx_size, true,
5407 rx_q->dma_rx_phy, desc_size);
5409 while (count < limit) {
5410 unsigned int buf1_len = 0, buf2_len = 0;
5411 enum pkt_hash_types hash_type;
5412 struct stmmac_rx_buffer *buf;
5413 struct dma_desc *np, *p;
5417 if (!count && rx_q->state_saved) {
5418 skb = rx_q->state.skb;
5419 error = rx_q->state.error;
5420 len = rx_q->state.len;
5422 rx_q->state_saved = false;
5435 buf = &rx_q->buf_pool[entry];
5437 if (priv->extend_desc)
5438 p = (struct dma_desc *)(rx_q->dma_erx + entry);
5440 p = rx_q->dma_rx + entry;
5442 /* read the status of the incoming frame */
5443 status = stmmac_rx_status(priv, &priv->xstats, p);
5444 /* check if managed by the DMA otherwise go ahead */
5445 if (unlikely(status & dma_own))
5448 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx,
5449 priv->dma_conf.dma_rx_size);
5450 next_entry = rx_q->cur_rx;
5452 if (priv->extend_desc)
5453 np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
5455 np = rx_q->dma_rx + next_entry;
5459 if (priv->extend_desc)
5460 stmmac_rx_extended_status(priv, &priv->xstats, rx_q->dma_erx + entry);
5461 if (unlikely(status == discard_frame)) {
5462 page_pool_recycle_direct(rx_q->page_pool, buf->page);
5465 if (!priv->hwts_rx_en)
5469 if (unlikely(error && (status & rx_not_ls)))
5471 if (unlikely(error)) {
5478 /* Buffer is good. Go on. */
5480 prefetch(page_address(buf->page) + buf->page_offset);
5482 prefetch(page_address(buf->sec_page));
5484 buf1_len = stmmac_rx_buf1_len(priv, p, status, len);
5486 buf2_len = stmmac_rx_buf2_len(priv, p, status, len);
5489 /* ACS is disabled; strip manually. */
5490 if (likely(!(status & rx_not_ls))) {
5492 buf2_len -= ETH_FCS_LEN;
5494 } else if (buf1_len) {
5495 buf1_len -= ETH_FCS_LEN;
5501 unsigned int pre_len, sync_len;
5503 dma_sync_single_for_cpu(priv->device, buf->addr,
5506 xdp_init_buff(&ctx.xdp, buf_sz, &rx_q->xdp_rxq);
5507 xdp_prepare_buff(&ctx.xdp, page_address(buf->page),
5508 buf->page_offset, buf1_len, true);
5510 pre_len = ctx.xdp.data_end - ctx.xdp.data_hard_start -
5517 skb = stmmac_xdp_run_prog(priv, &ctx.xdp);
5518 /* Due xdp_adjust_tail: DMA sync for_device
5519 * cover max len CPU touch
5521 sync_len = ctx.xdp.data_end - ctx.xdp.data_hard_start -
5523 sync_len = max(sync_len, pre_len);
5525 /* For Not XDP_PASS verdict */
5527 unsigned int xdp_res = -PTR_ERR(skb);
5529 if (xdp_res & STMMAC_XDP_CONSUMED) {
5530 page_pool_put_page(rx_q->page_pool,
5531 virt_to_head_page(ctx.xdp.data),
5536 /* Clear skb as it was set as
5537 * status by XDP program.
5541 if (unlikely((status & rx_not_ls)))
5546 } else if (xdp_res & (STMMAC_XDP_TX |
5547 STMMAC_XDP_REDIRECT)) {
5548 xdp_status |= xdp_res;
5558 /* XDP program may expand or reduce tail */
5559 buf1_len = ctx.xdp.data_end - ctx.xdp.data;
5561 skb = napi_alloc_skb(&ch->rx_napi, buf1_len);
5568 /* XDP program may adjust header */
5569 skb_copy_to_linear_data(skb, ctx.xdp.data, buf1_len);
5570 skb_put(skb, buf1_len);
5572 /* Data payload copied into SKB, page ready for recycle */
5573 page_pool_recycle_direct(rx_q->page_pool, buf->page);
5575 } else if (buf1_len) {
5576 dma_sync_single_for_cpu(priv->device, buf->addr,
5578 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
5579 buf->page, buf->page_offset, buf1_len,
5580 priv->dma_conf.dma_buf_sz);
5582 /* Data payload appended into SKB */
5583 skb_mark_for_recycle(skb);
5588 dma_sync_single_for_cpu(priv->device, buf->sec_addr,
5590 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
5591 buf->sec_page, 0, buf2_len,
5592 priv->dma_conf.dma_buf_sz);
5594 /* Data payload appended into SKB */
5595 skb_mark_for_recycle(skb);
5596 buf->sec_page = NULL;
5600 if (likely(status & rx_not_ls))
5605 /* Got entire packet into SKB. Finish it. */
5607 stmmac_get_rx_hwtstamp(priv, p, np, skb);
5609 if (priv->hw->hw_vlan_en)
5610 /* MAC level stripping. */
5611 stmmac_rx_hw_vlan(priv, priv->hw, p, skb);
5613 /* Driver level stripping. */
5614 stmmac_rx_vlan(priv->dev, skb);
5616 skb->protocol = eth_type_trans(skb, priv->dev);
5618 if (unlikely(!coe) || !stmmac_has_ip_ethertype(skb))
5619 skb_checksum_none_assert(skb);
5621 skb->ip_summed = CHECKSUM_UNNECESSARY;
5623 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type))
5624 skb_set_hash(skb, hash, hash_type);
5626 skb_record_rx_queue(skb, queue);
5627 napi_gro_receive(&ch->rx_napi, skb);
5635 if (status & rx_not_ls || skb) {
5636 rx_q->state_saved = true;
5637 rx_q->state.skb = skb;
5638 rx_q->state.error = error;
5639 rx_q->state.len = len;
5642 stmmac_finalize_xdp_rx(priv, xdp_status);
5644 stmmac_rx_refill(priv, queue);
5646 flags = u64_stats_update_begin_irqsave(&rxq_stats->syncp);
5647 rxq_stats->rx_packets += rx_packets;
5648 rxq_stats->rx_bytes += rx_bytes;
5649 rxq_stats->rx_pkt_n += count;
5650 u64_stats_update_end_irqrestore(&rxq_stats->syncp, flags);
5652 priv->xstats.rx_dropped += rx_dropped;
5653 priv->xstats.rx_errors += rx_errors;
5658 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget)
5660 struct stmmac_channel *ch =
5661 container_of(napi, struct stmmac_channel, rx_napi);
5662 struct stmmac_priv *priv = ch->priv_data;
5663 struct stmmac_rxq_stats *rxq_stats;
5664 u32 chan = ch->index;
5665 unsigned long flags;
5668 rxq_stats = &priv->xstats.rxq_stats[chan];
5669 flags = u64_stats_update_begin_irqsave(&rxq_stats->syncp);
5670 rxq_stats->napi_poll++;
5671 u64_stats_update_end_irqrestore(&rxq_stats->syncp, flags);
5673 work_done = stmmac_rx(priv, budget, chan);
5674 if (work_done < budget && napi_complete_done(napi, work_done)) {
5675 unsigned long flags;
5677 spin_lock_irqsave(&ch->lock, flags);
5678 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0);
5679 spin_unlock_irqrestore(&ch->lock, flags);
5685 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget)
5687 struct stmmac_channel *ch =
5688 container_of(napi, struct stmmac_channel, tx_napi);
5689 struct stmmac_priv *priv = ch->priv_data;
5690 struct stmmac_txq_stats *txq_stats;
5691 bool pending_packets = false;
5692 u32 chan = ch->index;
5693 unsigned long flags;
5696 txq_stats = &priv->xstats.txq_stats[chan];
5697 flags = u64_stats_update_begin_irqsave(&txq_stats->syncp);
5698 txq_stats->napi_poll++;
5699 u64_stats_update_end_irqrestore(&txq_stats->syncp, flags);
5701 work_done = stmmac_tx_clean(priv, budget, chan, &pending_packets);
5702 work_done = min(work_done, budget);
5704 if (work_done < budget && napi_complete_done(napi, work_done)) {
5705 unsigned long flags;
5707 spin_lock_irqsave(&ch->lock, flags);
5708 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1);
5709 spin_unlock_irqrestore(&ch->lock, flags);
5712 /* TX still have packet to handle, check if we need to arm tx timer */
5713 if (pending_packets)
5714 stmmac_tx_timer_arm(priv, chan);
5719 static int stmmac_napi_poll_rxtx(struct napi_struct *napi, int budget)
5721 struct stmmac_channel *ch =
5722 container_of(napi, struct stmmac_channel, rxtx_napi);
5723 struct stmmac_priv *priv = ch->priv_data;
5724 bool tx_pending_packets = false;
5725 int rx_done, tx_done, rxtx_done;
5726 struct stmmac_rxq_stats *rxq_stats;
5727 struct stmmac_txq_stats *txq_stats;
5728 u32 chan = ch->index;
5729 unsigned long flags;
5731 rxq_stats = &priv->xstats.rxq_stats[chan];
5732 flags = u64_stats_update_begin_irqsave(&rxq_stats->syncp);
5733 rxq_stats->napi_poll++;
5734 u64_stats_update_end_irqrestore(&rxq_stats->syncp, flags);
5736 txq_stats = &priv->xstats.txq_stats[chan];
5737 flags = u64_stats_update_begin_irqsave(&txq_stats->syncp);
5738 txq_stats->napi_poll++;
5739 u64_stats_update_end_irqrestore(&txq_stats->syncp, flags);
5741 tx_done = stmmac_tx_clean(priv, budget, chan, &tx_pending_packets);
5742 tx_done = min(tx_done, budget);
5744 rx_done = stmmac_rx_zc(priv, budget, chan);
5746 rxtx_done = max(tx_done, rx_done);
5748 /* If either TX or RX work is not complete, return budget
5751 if (rxtx_done >= budget)
5754 /* all work done, exit the polling mode */
5755 if (napi_complete_done(napi, rxtx_done)) {
5756 unsigned long flags;
5758 spin_lock_irqsave(&ch->lock, flags);
5759 /* Both RX and TX work done are compelte,
5760 * so enable both RX & TX IRQs.
5762 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1);
5763 spin_unlock_irqrestore(&ch->lock, flags);
5766 /* TX still have packet to handle, check if we need to arm tx timer */
5767 if (tx_pending_packets)
5768 stmmac_tx_timer_arm(priv, chan);
5770 return min(rxtx_done, budget - 1);
5775 * @dev : Pointer to net device structure
5776 * @txqueue: the index of the hanging transmit queue
5777 * Description: this function is called when a packet transmission fails to
5778 * complete within a reasonable time. The driver will mark the error in the
5779 * netdev structure and arrange for the device to be reset to a sane state
5780 * in order to transmit a new packet.
5782 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue)
5784 struct stmmac_priv *priv = netdev_priv(dev);
5786 stmmac_global_err(priv);
5790 * stmmac_set_rx_mode - entry point for multicast addressing
5791 * @dev : pointer to the device structure
5793 * This function is a driver entry point which gets called by the kernel
5794 * whenever multicast addresses must be enabled/disabled.
5798 static void stmmac_set_rx_mode(struct net_device *dev)
5800 struct stmmac_priv *priv = netdev_priv(dev);
5802 stmmac_set_filter(priv, priv->hw, dev);
5806 * stmmac_change_mtu - entry point to change MTU size for the device.
5807 * @dev : device pointer.
5808 * @new_mtu : the new MTU size for the device.
5809 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
5810 * to drive packet transmission. Ethernet has an MTU of 1500 octets
5811 * (ETH_DATA_LEN). This value can be changed with ifconfig.
5813 * 0 on success and an appropriate (-)ve integer as defined in errno.h
5816 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
5818 struct stmmac_priv *priv = netdev_priv(dev);
5819 int txfifosz = priv->plat->tx_fifo_size;
5820 struct stmmac_dma_conf *dma_conf;
5821 const int mtu = new_mtu;
5825 txfifosz = priv->dma_cap.tx_fifo_size;
5827 txfifosz /= priv->plat->tx_queues_to_use;
5829 if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) {
5830 netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n");
5834 new_mtu = STMMAC_ALIGN(new_mtu);
5836 /* If condition true, FIFO is too small or MTU too large */
5837 if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB))
5840 if (netif_running(dev)) {
5841 netdev_dbg(priv->dev, "restarting interface to change its MTU\n");
5842 /* Try to allocate the new DMA conf with the new mtu */
5843 dma_conf = stmmac_setup_dma_desc(priv, mtu);
5844 if (IS_ERR(dma_conf)) {
5845 netdev_err(priv->dev, "failed allocating new dma conf for new MTU %d\n",
5847 return PTR_ERR(dma_conf);
5850 stmmac_release(dev);
5852 ret = __stmmac_open(dev, dma_conf);
5854 free_dma_desc_resources(priv, dma_conf);
5856 netdev_err(priv->dev, "failed reopening the interface after MTU change\n");
5862 stmmac_set_rx_mode(dev);
5866 netdev_update_features(dev);
5871 static netdev_features_t stmmac_fix_features(struct net_device *dev,
5872 netdev_features_t features)
5874 struct stmmac_priv *priv = netdev_priv(dev);
5876 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
5877 features &= ~NETIF_F_RXCSUM;
5879 if (!priv->plat->tx_coe)
5880 features &= ~NETIF_F_CSUM_MASK;
5882 /* Some GMAC devices have a bugged Jumbo frame support that
5883 * needs to have the Tx COE disabled for oversized frames
5884 * (due to limited buffer sizes). In this case we disable
5885 * the TX csum insertion in the TDES and not use SF.
5887 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
5888 features &= ~NETIF_F_CSUM_MASK;
5890 /* Disable tso if asked by ethtool */
5891 if ((priv->plat->flags & STMMAC_FLAG_TSO_EN) && (priv->dma_cap.tsoen)) {
5892 if (features & NETIF_F_TSO)
5901 static int stmmac_set_features(struct net_device *netdev,
5902 netdev_features_t features)
5904 struct stmmac_priv *priv = netdev_priv(netdev);
5906 /* Keep the COE Type in case of csum is supporting */
5907 if (features & NETIF_F_RXCSUM)
5908 priv->hw->rx_csum = priv->plat->rx_coe;
5910 priv->hw->rx_csum = 0;
5911 /* No check needed because rx_coe has been set before and it will be
5912 * fixed in case of issue.
5914 stmmac_rx_ipc(priv, priv->hw);
5916 if (priv->sph_cap) {
5917 bool sph_en = (priv->hw->rx_csum > 0) && priv->sph;
5920 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++)
5921 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
5924 if (features & NETIF_F_HW_VLAN_CTAG_RX)
5925 priv->hw->hw_vlan_en = true;
5927 priv->hw->hw_vlan_en = false;
5929 stmmac_set_hw_vlan_mode(priv, priv->hw);
5934 static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status)
5936 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
5937 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
5938 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
5939 bool *hs_enable = &fpe_cfg->hs_enable;
5941 if (status == FPE_EVENT_UNKNOWN || !*hs_enable)
5944 /* If LP has sent verify mPacket, LP is FPE capable */
5945 if ((status & FPE_EVENT_RVER) == FPE_EVENT_RVER) {
5946 if (*lp_state < FPE_STATE_CAPABLE)
5947 *lp_state = FPE_STATE_CAPABLE;
5949 /* If user has requested FPE enable, quickly response */
5951 stmmac_fpe_send_mpacket(priv, priv->ioaddr,
5956 /* If Local has sent verify mPacket, Local is FPE capable */
5957 if ((status & FPE_EVENT_TVER) == FPE_EVENT_TVER) {
5958 if (*lo_state < FPE_STATE_CAPABLE)
5959 *lo_state = FPE_STATE_CAPABLE;
5962 /* If LP has sent response mPacket, LP is entering FPE ON */
5963 if ((status & FPE_EVENT_RRSP) == FPE_EVENT_RRSP)
5964 *lp_state = FPE_STATE_ENTERING_ON;
5966 /* If Local has sent response mPacket, Local is entering FPE ON */
5967 if ((status & FPE_EVENT_TRSP) == FPE_EVENT_TRSP)
5968 *lo_state = FPE_STATE_ENTERING_ON;
5970 if (!test_bit(__FPE_REMOVING, &priv->fpe_task_state) &&
5971 !test_and_set_bit(__FPE_TASK_SCHED, &priv->fpe_task_state) &&
5973 queue_work(priv->fpe_wq, &priv->fpe_task);
5977 static void stmmac_common_interrupt(struct stmmac_priv *priv)
5979 u32 rx_cnt = priv->plat->rx_queues_to_use;
5980 u32 tx_cnt = priv->plat->tx_queues_to_use;
5985 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
5986 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
5989 pm_wakeup_event(priv->device, 0);
5991 if (priv->dma_cap.estsel)
5992 stmmac_est_irq_status(priv, priv, priv->dev,
5993 &priv->xstats, tx_cnt);
5995 if (priv->dma_cap.fpesel) {
5996 int status = stmmac_fpe_irq_status(priv, priv->ioaddr,
5999 stmmac_fpe_event_status(priv, status);
6002 /* To handle GMAC own interrupts */
6003 if ((priv->plat->has_gmac) || xmac) {
6004 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
6006 if (unlikely(status)) {
6007 /* For LPI we need to save the tx status */
6008 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
6009 priv->tx_path_in_lpi_mode = true;
6010 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
6011 priv->tx_path_in_lpi_mode = false;
6014 for (queue = 0; queue < queues_count; queue++) {
6015 status = stmmac_host_mtl_irq_status(priv, priv->hw,
6019 /* PCS link status */
6020 if (priv->hw->pcs &&
6021 !(priv->plat->flags & STMMAC_FLAG_HAS_INTEGRATED_PCS)) {
6022 if (priv->xstats.pcs_link)
6023 netif_carrier_on(priv->dev);
6025 netif_carrier_off(priv->dev);
6028 stmmac_timestamp_interrupt(priv, priv);
6033 * stmmac_interrupt - main ISR
6034 * @irq: interrupt number.
6035 * @dev_id: to pass the net device pointer.
6036 * Description: this is the main driver interrupt service routine.
6038 * o DMA service routine (to manage incoming frame reception and transmission
6040 * o Core interrupts to manage: remote wake-up, management counter, LPI
6043 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
6045 struct net_device *dev = (struct net_device *)dev_id;
6046 struct stmmac_priv *priv = netdev_priv(dev);
6048 /* Check if adapter is up */
6049 if (test_bit(STMMAC_DOWN, &priv->state))
6052 /* Check if a fatal error happened */
6053 if (stmmac_safety_feat_interrupt(priv))
6056 /* To handle Common interrupts */
6057 stmmac_common_interrupt(priv);
6059 /* To handle DMA interrupts */
6060 stmmac_dma_interrupt(priv);
6065 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id)
6067 struct net_device *dev = (struct net_device *)dev_id;
6068 struct stmmac_priv *priv = netdev_priv(dev);
6070 if (unlikely(!dev)) {
6071 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
6075 /* Check if adapter is up */
6076 if (test_bit(STMMAC_DOWN, &priv->state))
6079 /* To handle Common interrupts */
6080 stmmac_common_interrupt(priv);
6085 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id)
6087 struct net_device *dev = (struct net_device *)dev_id;
6088 struct stmmac_priv *priv = netdev_priv(dev);
6090 if (unlikely(!dev)) {
6091 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
6095 /* Check if adapter is up */
6096 if (test_bit(STMMAC_DOWN, &priv->state))
6099 /* Check if a fatal error happened */
6100 stmmac_safety_feat_interrupt(priv);
6105 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data)
6107 struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data;
6108 struct stmmac_dma_conf *dma_conf;
6109 int chan = tx_q->queue_index;
6110 struct stmmac_priv *priv;
6113 dma_conf = container_of(tx_q, struct stmmac_dma_conf, tx_queue[chan]);
6114 priv = container_of(dma_conf, struct stmmac_priv, dma_conf);
6116 if (unlikely(!data)) {
6117 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
6121 /* Check if adapter is up */
6122 if (test_bit(STMMAC_DOWN, &priv->state))
6125 status = stmmac_napi_check(priv, chan, DMA_DIR_TX);
6127 if (unlikely(status & tx_hard_error_bump_tc)) {
6128 /* Try to bump up the dma threshold on this failure */
6129 stmmac_bump_dma_threshold(priv, chan);
6130 } else if (unlikely(status == tx_hard_error)) {
6131 stmmac_tx_err(priv, chan);
6137 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data)
6139 struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data;
6140 struct stmmac_dma_conf *dma_conf;
6141 int chan = rx_q->queue_index;
6142 struct stmmac_priv *priv;
6144 dma_conf = container_of(rx_q, struct stmmac_dma_conf, rx_queue[chan]);
6145 priv = container_of(dma_conf, struct stmmac_priv, dma_conf);
6147 if (unlikely(!data)) {
6148 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
6152 /* Check if adapter is up */
6153 if (test_bit(STMMAC_DOWN, &priv->state))
6156 stmmac_napi_check(priv, chan, DMA_DIR_RX);
6162 * stmmac_ioctl - Entry point for the Ioctl
6163 * @dev: Device pointer.
6164 * @rq: An IOCTL specefic structure, that can contain a pointer to
6165 * a proprietary structure used to pass information to the driver.
6166 * @cmd: IOCTL command
6168 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
6170 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
6172 struct stmmac_priv *priv = netdev_priv (dev);
6173 int ret = -EOPNOTSUPP;
6175 if (!netif_running(dev))
6182 ret = phylink_mii_ioctl(priv->phylink, rq, cmd);
6185 ret = stmmac_hwtstamp_set(dev, rq);
6188 ret = stmmac_hwtstamp_get(dev, rq);
6197 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
6200 struct stmmac_priv *priv = cb_priv;
6201 int ret = -EOPNOTSUPP;
6203 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data))
6206 __stmmac_disable_all_queues(priv);
6209 case TC_SETUP_CLSU32:
6210 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data);
6212 case TC_SETUP_CLSFLOWER:
6213 ret = stmmac_tc_setup_cls(priv, priv, type_data);
6219 stmmac_enable_all_queues(priv);
6223 static LIST_HEAD(stmmac_block_cb_list);
6225 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
6228 struct stmmac_priv *priv = netdev_priv(ndev);
6232 return stmmac_tc_query_caps(priv, priv, type_data);
6233 case TC_SETUP_BLOCK:
6234 return flow_block_cb_setup_simple(type_data,
6235 &stmmac_block_cb_list,
6236 stmmac_setup_tc_block_cb,
6238 case TC_SETUP_QDISC_CBS:
6239 return stmmac_tc_setup_cbs(priv, priv, type_data);
6240 case TC_SETUP_QDISC_TAPRIO:
6241 return stmmac_tc_setup_taprio(priv, priv, type_data);
6242 case TC_SETUP_QDISC_ETF:
6243 return stmmac_tc_setup_etf(priv, priv, type_data);
6249 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb,
6250 struct net_device *sb_dev)
6252 int gso = skb_shinfo(skb)->gso_type;
6254 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) {
6256 * There is no way to determine the number of TSO/USO
6257 * capable Queues. Let's use always the Queue 0
6258 * because if TSO/USO is supported then at least this
6259 * one will be capable.
6264 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues;
6267 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
6269 struct stmmac_priv *priv = netdev_priv(ndev);
6272 ret = pm_runtime_resume_and_get(priv->device);
6276 ret = eth_mac_addr(ndev, addr);
6280 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
6283 pm_runtime_put(priv->device);
6288 #ifdef CONFIG_DEBUG_FS
6289 static struct dentry *stmmac_fs_dir;
6291 static void sysfs_display_ring(void *head, int size, int extend_desc,
6292 struct seq_file *seq, dma_addr_t dma_phy_addr)
6294 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
6295 struct dma_desc *p = (struct dma_desc *)head;
6296 unsigned int desc_size;
6297 dma_addr_t dma_addr;
6300 desc_size = extend_desc ? sizeof(*ep) : sizeof(*p);
6301 for (i = 0; i < size; i++) {
6302 dma_addr = dma_phy_addr + i * desc_size;
6303 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",
6305 le32_to_cpu(p->des0), le32_to_cpu(p->des1),
6306 le32_to_cpu(p->des2), le32_to_cpu(p->des3));
6314 static int stmmac_rings_status_show(struct seq_file *seq, void *v)
6316 struct net_device *dev = seq->private;
6317 struct stmmac_priv *priv = netdev_priv(dev);
6318 u32 rx_count = priv->plat->rx_queues_to_use;
6319 u32 tx_count = priv->plat->tx_queues_to_use;
6322 if ((dev->flags & IFF_UP) == 0)
6325 for (queue = 0; queue < rx_count; queue++) {
6326 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
6328 seq_printf(seq, "RX Queue %d:\n", queue);
6330 if (priv->extend_desc) {
6331 seq_printf(seq, "Extended descriptor ring:\n");
6332 sysfs_display_ring((void *)rx_q->dma_erx,
6333 priv->dma_conf.dma_rx_size, 1, seq, rx_q->dma_rx_phy);
6335 seq_printf(seq, "Descriptor ring:\n");
6336 sysfs_display_ring((void *)rx_q->dma_rx,
6337 priv->dma_conf.dma_rx_size, 0, seq, rx_q->dma_rx_phy);
6341 for (queue = 0; queue < tx_count; queue++) {
6342 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
6344 seq_printf(seq, "TX Queue %d:\n", queue);
6346 if (priv->extend_desc) {
6347 seq_printf(seq, "Extended descriptor ring:\n");
6348 sysfs_display_ring((void *)tx_q->dma_etx,
6349 priv->dma_conf.dma_tx_size, 1, seq, tx_q->dma_tx_phy);
6350 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) {
6351 seq_printf(seq, "Descriptor ring:\n");
6352 sysfs_display_ring((void *)tx_q->dma_tx,
6353 priv->dma_conf.dma_tx_size, 0, seq, tx_q->dma_tx_phy);
6359 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status);
6361 static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
6363 static const char * const dwxgmac_timestamp_source[] = {
6369 static const char * const dwxgmac_safety_feature_desc[] = {
6371 "All Safety Features with ECC and Parity",
6372 "All Safety Features without ECC or Parity",
6373 "All Safety Features with Parity Only",
6379 struct net_device *dev = seq->private;
6380 struct stmmac_priv *priv = netdev_priv(dev);
6382 if (!priv->hw_cap_support) {
6383 seq_printf(seq, "DMA HW features not supported\n");
6387 seq_printf(seq, "==============================\n");
6388 seq_printf(seq, "\tDMA HW features\n");
6389 seq_printf(seq, "==============================\n");
6391 seq_printf(seq, "\t10/100 Mbps: %s\n",
6392 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
6393 seq_printf(seq, "\t1000 Mbps: %s\n",
6394 (priv->dma_cap.mbps_1000) ? "Y" : "N");
6395 seq_printf(seq, "\tHalf duplex: %s\n",
6396 (priv->dma_cap.half_duplex) ? "Y" : "N");
6397 if (priv->plat->has_xgmac) {
6399 "\tNumber of Additional MAC address registers: %d\n",
6400 priv->dma_cap.multi_addr);
6402 seq_printf(seq, "\tHash Filter: %s\n",
6403 (priv->dma_cap.hash_filter) ? "Y" : "N");
6404 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
6405 (priv->dma_cap.multi_addr) ? "Y" : "N");
6407 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
6408 (priv->dma_cap.pcs) ? "Y" : "N");
6409 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
6410 (priv->dma_cap.sma_mdio) ? "Y" : "N");
6411 seq_printf(seq, "\tPMT Remote wake up: %s\n",
6412 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
6413 seq_printf(seq, "\tPMT Magic Frame: %s\n",
6414 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
6415 seq_printf(seq, "\tRMON module: %s\n",
6416 (priv->dma_cap.rmon) ? "Y" : "N");
6417 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
6418 (priv->dma_cap.time_stamp) ? "Y" : "N");
6419 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
6420 (priv->dma_cap.atime_stamp) ? "Y" : "N");
6421 if (priv->plat->has_xgmac)
6422 seq_printf(seq, "\tTimestamp System Time Source: %s\n",
6423 dwxgmac_timestamp_source[priv->dma_cap.tssrc]);
6424 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
6425 (priv->dma_cap.eee) ? "Y" : "N");
6426 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
6427 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
6428 (priv->dma_cap.tx_coe) ? "Y" : "N");
6429 if (priv->synopsys_id >= DWMAC_CORE_4_00 ||
6430 priv->plat->has_xgmac) {
6431 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
6432 (priv->dma_cap.rx_coe) ? "Y" : "N");
6434 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
6435 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
6436 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
6437 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
6438 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
6439 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
6441 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
6442 priv->dma_cap.number_rx_channel);
6443 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
6444 priv->dma_cap.number_tx_channel);
6445 seq_printf(seq, "\tNumber of Additional RX queues: %d\n",
6446 priv->dma_cap.number_rx_queues);
6447 seq_printf(seq, "\tNumber of Additional TX queues: %d\n",
6448 priv->dma_cap.number_tx_queues);
6449 seq_printf(seq, "\tEnhanced descriptors: %s\n",
6450 (priv->dma_cap.enh_desc) ? "Y" : "N");
6451 seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size);
6452 seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size);
6453 seq_printf(seq, "\tHash Table Size: %lu\n", priv->dma_cap.hash_tb_sz ?
6454 (BIT(priv->dma_cap.hash_tb_sz) << 5) : 0);
6455 seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N");
6456 seq_printf(seq, "\tNumber of PPS Outputs: %d\n",
6457 priv->dma_cap.pps_out_num);
6458 seq_printf(seq, "\tSafety Features: %s\n",
6459 dwxgmac_safety_feature_desc[priv->dma_cap.asp]);
6460 seq_printf(seq, "\tFlexible RX Parser: %s\n",
6461 priv->dma_cap.frpsel ? "Y" : "N");
6462 seq_printf(seq, "\tEnhanced Addressing: %d\n",
6463 priv->dma_cap.host_dma_width);
6464 seq_printf(seq, "\tReceive Side Scaling: %s\n",
6465 priv->dma_cap.rssen ? "Y" : "N");
6466 seq_printf(seq, "\tVLAN Hash Filtering: %s\n",
6467 priv->dma_cap.vlhash ? "Y" : "N");
6468 seq_printf(seq, "\tSplit Header: %s\n",
6469 priv->dma_cap.sphen ? "Y" : "N");
6470 seq_printf(seq, "\tVLAN TX Insertion: %s\n",
6471 priv->dma_cap.vlins ? "Y" : "N");
6472 seq_printf(seq, "\tDouble VLAN: %s\n",
6473 priv->dma_cap.dvlan ? "Y" : "N");
6474 seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n",
6475 priv->dma_cap.l3l4fnum);
6476 seq_printf(seq, "\tARP Offloading: %s\n",
6477 priv->dma_cap.arpoffsel ? "Y" : "N");
6478 seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n",
6479 priv->dma_cap.estsel ? "Y" : "N");
6480 seq_printf(seq, "\tFrame Preemption (FPE): %s\n",
6481 priv->dma_cap.fpesel ? "Y" : "N");
6482 seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n",
6483 priv->dma_cap.tbssel ? "Y" : "N");
6484 seq_printf(seq, "\tNumber of DMA Channels Enabled for TBS: %d\n",
6485 priv->dma_cap.tbs_ch_num);
6486 seq_printf(seq, "\tPer-Stream Filtering: %s\n",
6487 priv->dma_cap.sgfsel ? "Y" : "N");
6488 seq_printf(seq, "\tTX Timestamp FIFO Depth: %lu\n",
6489 BIT(priv->dma_cap.ttsfd) >> 1);
6490 seq_printf(seq, "\tNumber of Traffic Classes: %d\n",
6491 priv->dma_cap.numtc);
6492 seq_printf(seq, "\tDCB Feature: %s\n",
6493 priv->dma_cap.dcben ? "Y" : "N");
6494 seq_printf(seq, "\tIEEE 1588 High Word Register: %s\n",
6495 priv->dma_cap.advthword ? "Y" : "N");
6496 seq_printf(seq, "\tPTP Offload: %s\n",
6497 priv->dma_cap.ptoen ? "Y" : "N");
6498 seq_printf(seq, "\tOne-Step Timestamping: %s\n",
6499 priv->dma_cap.osten ? "Y" : "N");
6500 seq_printf(seq, "\tPriority-Based Flow Control: %s\n",
6501 priv->dma_cap.pfcen ? "Y" : "N");
6502 seq_printf(seq, "\tNumber of Flexible RX Parser Instructions: %lu\n",
6503 BIT(priv->dma_cap.frpes) << 6);
6504 seq_printf(seq, "\tNumber of Flexible RX Parser Parsable Bytes: %lu\n",
6505 BIT(priv->dma_cap.frpbs) << 6);
6506 seq_printf(seq, "\tParallel Instruction Processor Engines: %d\n",
6507 priv->dma_cap.frppipe_num);
6508 seq_printf(seq, "\tNumber of Extended VLAN Tag Filters: %lu\n",
6509 priv->dma_cap.nrvf_num ?
6510 (BIT(priv->dma_cap.nrvf_num) << 1) : 0);
6511 seq_printf(seq, "\tWidth of the Time Interval Field in GCL: %d\n",
6512 priv->dma_cap.estwid ? 4 * priv->dma_cap.estwid + 12 : 0);
6513 seq_printf(seq, "\tDepth of GCL: %lu\n",
6514 priv->dma_cap.estdep ? (BIT(priv->dma_cap.estdep) << 5) : 0);
6515 seq_printf(seq, "\tQueue/Channel-Based VLAN Tag Insertion on TX: %s\n",
6516 priv->dma_cap.cbtisel ? "Y" : "N");
6517 seq_printf(seq, "\tNumber of Auxiliary Snapshot Inputs: %d\n",
6518 priv->dma_cap.aux_snapshot_n);
6519 seq_printf(seq, "\tOne-Step Timestamping for PTP over UDP/IP: %s\n",
6520 priv->dma_cap.pou_ost_en ? "Y" : "N");
6521 seq_printf(seq, "\tEnhanced DMA: %s\n",
6522 priv->dma_cap.edma ? "Y" : "N");
6523 seq_printf(seq, "\tDifferent Descriptor Cache: %s\n",
6524 priv->dma_cap.ediffc ? "Y" : "N");
6525 seq_printf(seq, "\tVxLAN/NVGRE: %s\n",
6526 priv->dma_cap.vxn ? "Y" : "N");
6527 seq_printf(seq, "\tDebug Memory Interface: %s\n",
6528 priv->dma_cap.dbgmem ? "Y" : "N");
6529 seq_printf(seq, "\tNumber of Policing Counters: %lu\n",
6530 priv->dma_cap.pcsel ? BIT(priv->dma_cap.pcsel + 3) : 0);
6533 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap);
6535 /* Use network device events to rename debugfs file entries.
6537 static int stmmac_device_event(struct notifier_block *unused,
6538 unsigned long event, void *ptr)
6540 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
6541 struct stmmac_priv *priv = netdev_priv(dev);
6543 if (dev->netdev_ops != &stmmac_netdev_ops)
6547 case NETDEV_CHANGENAME:
6548 if (priv->dbgfs_dir)
6549 priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir,
6559 static struct notifier_block stmmac_notifier = {
6560 .notifier_call = stmmac_device_event,
6563 static void stmmac_init_fs(struct net_device *dev)
6565 struct stmmac_priv *priv = netdev_priv(dev);
6569 /* Create per netdev entries */
6570 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
6572 /* Entry to report DMA RX/TX rings */
6573 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev,
6574 &stmmac_rings_status_fops);
6576 /* Entry to report the DMA HW features */
6577 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev,
6578 &stmmac_dma_cap_fops);
6583 static void stmmac_exit_fs(struct net_device *dev)
6585 struct stmmac_priv *priv = netdev_priv(dev);
6587 debugfs_remove_recursive(priv->dbgfs_dir);
6589 #endif /* CONFIG_DEBUG_FS */
6591 static u32 stmmac_vid_crc32_le(__le16 vid_le)
6593 unsigned char *data = (unsigned char *)&vid_le;
6594 unsigned char data_byte = 0;
6599 bits = get_bitmask_order(VLAN_VID_MASK);
6600 for (i = 0; i < bits; i++) {
6602 data_byte = data[i / 8];
6604 temp = ((crc & 1) ^ data_byte) & 1;
6615 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double)
6622 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
6623 __le16 vid_le = cpu_to_le16(vid);
6624 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28;
6629 if (!priv->dma_cap.vlhash) {
6630 if (count > 2) /* VID = 0 always passes filter */
6633 pmatch = cpu_to_le16(vid);
6637 return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double);
6640 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)
6642 struct stmmac_priv *priv = netdev_priv(ndev);
6643 bool is_double = false;
6646 ret = pm_runtime_resume_and_get(priv->device);
6650 if (be16_to_cpu(proto) == ETH_P_8021AD)
6653 set_bit(vid, priv->active_vlans);
6654 ret = stmmac_vlan_update(priv, is_double);
6656 clear_bit(vid, priv->active_vlans);
6660 if (priv->hw->num_vlan) {
6661 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid);
6666 pm_runtime_put(priv->device);
6671 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid)
6673 struct stmmac_priv *priv = netdev_priv(ndev);
6674 bool is_double = false;
6677 ret = pm_runtime_resume_and_get(priv->device);
6681 if (be16_to_cpu(proto) == ETH_P_8021AD)
6684 clear_bit(vid, priv->active_vlans);
6686 if (priv->hw->num_vlan) {
6687 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid);
6689 goto del_vlan_error;
6692 ret = stmmac_vlan_update(priv, is_double);
6695 pm_runtime_put(priv->device);
6700 static int stmmac_bpf(struct net_device *dev, struct netdev_bpf *bpf)
6702 struct stmmac_priv *priv = netdev_priv(dev);
6704 switch (bpf->command) {
6705 case XDP_SETUP_PROG:
6706 return stmmac_xdp_set_prog(priv, bpf->prog, bpf->extack);
6707 case XDP_SETUP_XSK_POOL:
6708 return stmmac_xdp_setup_pool(priv, bpf->xsk.pool,
6715 static int stmmac_xdp_xmit(struct net_device *dev, int num_frames,
6716 struct xdp_frame **frames, u32 flags)
6718 struct stmmac_priv *priv = netdev_priv(dev);
6719 int cpu = smp_processor_id();
6720 struct netdev_queue *nq;
6724 if (unlikely(test_bit(STMMAC_DOWN, &priv->state)))
6727 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
6730 queue = stmmac_xdp_get_tx_queue(priv, cpu);
6731 nq = netdev_get_tx_queue(priv->dev, queue);
6733 __netif_tx_lock(nq, cpu);
6734 /* Avoids TX time-out as we are sharing with slow path */
6735 txq_trans_cond_update(nq);
6737 for (i = 0; i < num_frames; i++) {
6740 res = stmmac_xdp_xmit_xdpf(priv, queue, frames[i], true);
6741 if (res == STMMAC_XDP_CONSUMED)
6747 if (flags & XDP_XMIT_FLUSH) {
6748 stmmac_flush_tx_descriptors(priv, queue);
6749 stmmac_tx_timer_arm(priv, queue);
6752 __netif_tx_unlock(nq);
6757 void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue)
6759 struct stmmac_channel *ch = &priv->channel[queue];
6760 unsigned long flags;
6762 spin_lock_irqsave(&ch->lock, flags);
6763 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 1, 0);
6764 spin_unlock_irqrestore(&ch->lock, flags);
6766 stmmac_stop_rx_dma(priv, queue);
6767 __free_dma_rx_desc_resources(priv, &priv->dma_conf, queue);
6770 void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue)
6772 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
6773 struct stmmac_channel *ch = &priv->channel[queue];
6774 unsigned long flags;
6778 ret = __alloc_dma_rx_desc_resources(priv, &priv->dma_conf, queue);
6780 netdev_err(priv->dev, "Failed to alloc RX desc.\n");
6784 ret = __init_dma_rx_desc_rings(priv, &priv->dma_conf, queue, GFP_KERNEL);
6786 __free_dma_rx_desc_resources(priv, &priv->dma_conf, queue);
6787 netdev_err(priv->dev, "Failed to init RX desc.\n");
6791 stmmac_reset_rx_queue(priv, queue);
6792 stmmac_clear_rx_descriptors(priv, &priv->dma_conf, queue);
6794 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6795 rx_q->dma_rx_phy, rx_q->queue_index);
6797 rx_q->rx_tail_addr = rx_q->dma_rx_phy + (rx_q->buf_alloc_num *
6798 sizeof(struct dma_desc));
6799 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
6800 rx_q->rx_tail_addr, rx_q->queue_index);
6802 if (rx_q->xsk_pool && rx_q->buf_alloc_num) {
6803 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool);
6804 stmmac_set_dma_bfsize(priv, priv->ioaddr,
6808 stmmac_set_dma_bfsize(priv, priv->ioaddr,
6809 priv->dma_conf.dma_buf_sz,
6813 stmmac_start_rx_dma(priv, queue);
6815 spin_lock_irqsave(&ch->lock, flags);
6816 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 1, 0);
6817 spin_unlock_irqrestore(&ch->lock, flags);
6820 void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue)
6822 struct stmmac_channel *ch = &priv->channel[queue];
6823 unsigned long flags;
6825 spin_lock_irqsave(&ch->lock, flags);
6826 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 0, 1);
6827 spin_unlock_irqrestore(&ch->lock, flags);
6829 stmmac_stop_tx_dma(priv, queue);
6830 __free_dma_tx_desc_resources(priv, &priv->dma_conf, queue);
6833 void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue)
6835 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
6836 struct stmmac_channel *ch = &priv->channel[queue];
6837 unsigned long flags;
6840 ret = __alloc_dma_tx_desc_resources(priv, &priv->dma_conf, queue);
6842 netdev_err(priv->dev, "Failed to alloc TX desc.\n");
6846 ret = __init_dma_tx_desc_rings(priv, &priv->dma_conf, queue);
6848 __free_dma_tx_desc_resources(priv, &priv->dma_conf, queue);
6849 netdev_err(priv->dev, "Failed to init TX desc.\n");
6853 stmmac_reset_tx_queue(priv, queue);
6854 stmmac_clear_tx_descriptors(priv, &priv->dma_conf, queue);
6856 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6857 tx_q->dma_tx_phy, tx_q->queue_index);
6859 if (tx_q->tbs & STMMAC_TBS_AVAIL)
6860 stmmac_enable_tbs(priv, priv->ioaddr, 1, tx_q->queue_index);
6862 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
6863 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
6864 tx_q->tx_tail_addr, tx_q->queue_index);
6866 stmmac_start_tx_dma(priv, queue);
6868 spin_lock_irqsave(&ch->lock, flags);
6869 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 0, 1);
6870 spin_unlock_irqrestore(&ch->lock, flags);
6873 void stmmac_xdp_release(struct net_device *dev)
6875 struct stmmac_priv *priv = netdev_priv(dev);
6878 /* Ensure tx function is not running */
6879 netif_tx_disable(dev);
6881 /* Disable NAPI process */
6882 stmmac_disable_all_queues(priv);
6884 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
6885 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer);
6887 /* Free the IRQ lines */
6888 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0);
6890 /* Stop TX/RX DMA channels */
6891 stmmac_stop_all_dma(priv);
6893 /* Release and free the Rx/Tx resources */
6894 free_dma_desc_resources(priv, &priv->dma_conf);
6896 /* Disable the MAC Rx/Tx */
6897 stmmac_mac_set(priv, priv->ioaddr, false);
6899 /* set trans_start so we don't get spurious
6900 * watchdogs during reset
6902 netif_trans_update(dev);
6903 netif_carrier_off(dev);
6906 int stmmac_xdp_open(struct net_device *dev)
6908 struct stmmac_priv *priv = netdev_priv(dev);
6909 u32 rx_cnt = priv->plat->rx_queues_to_use;
6910 u32 tx_cnt = priv->plat->tx_queues_to_use;
6911 u32 dma_csr_ch = max(rx_cnt, tx_cnt);
6912 struct stmmac_rx_queue *rx_q;
6913 struct stmmac_tx_queue *tx_q;
6919 ret = alloc_dma_desc_resources(priv, &priv->dma_conf);
6921 netdev_err(dev, "%s: DMA descriptors allocation failed\n",
6923 goto dma_desc_error;
6926 ret = init_dma_desc_rings(dev, &priv->dma_conf, GFP_KERNEL);
6928 netdev_err(dev, "%s: DMA descriptors initialization failed\n",
6933 stmmac_reset_queues_param(priv);
6935 /* DMA CSR Channel configuration */
6936 for (chan = 0; chan < dma_csr_ch; chan++) {
6937 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
6938 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1);
6941 /* Adjust Split header */
6942 sph_en = (priv->hw->rx_csum > 0) && priv->sph;
6944 /* DMA RX Channel Configuration */
6945 for (chan = 0; chan < rx_cnt; chan++) {
6946 rx_q = &priv->dma_conf.rx_queue[chan];
6948 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6949 rx_q->dma_rx_phy, chan);
6951 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
6952 (rx_q->buf_alloc_num *
6953 sizeof(struct dma_desc));
6954 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
6955 rx_q->rx_tail_addr, chan);
6957 if (rx_q->xsk_pool && rx_q->buf_alloc_num) {
6958 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool);
6959 stmmac_set_dma_bfsize(priv, priv->ioaddr,
6963 stmmac_set_dma_bfsize(priv, priv->ioaddr,
6964 priv->dma_conf.dma_buf_sz,
6968 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
6971 /* DMA TX Channel Configuration */
6972 for (chan = 0; chan < tx_cnt; chan++) {
6973 tx_q = &priv->dma_conf.tx_queue[chan];
6975 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6976 tx_q->dma_tx_phy, chan);
6978 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
6979 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
6980 tx_q->tx_tail_addr, chan);
6982 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
6983 tx_q->txtimer.function = stmmac_tx_timer;
6986 /* Enable the MAC Rx/Tx */
6987 stmmac_mac_set(priv, priv->ioaddr, true);
6989 /* Start Rx & Tx DMA Channels */
6990 stmmac_start_all_dma(priv);
6992 ret = stmmac_request_irq(dev);
6996 /* Enable NAPI process*/
6997 stmmac_enable_all_queues(priv);
6998 netif_carrier_on(dev);
6999 netif_tx_start_all_queues(dev);
7000 stmmac_enable_all_dma_irq(priv);
7005 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
7006 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer);
7008 stmmac_hw_teardown(dev);
7010 free_dma_desc_resources(priv, &priv->dma_conf);
7015 int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags)
7017 struct stmmac_priv *priv = netdev_priv(dev);
7018 struct stmmac_rx_queue *rx_q;
7019 struct stmmac_tx_queue *tx_q;
7020 struct stmmac_channel *ch;
7022 if (test_bit(STMMAC_DOWN, &priv->state) ||
7023 !netif_carrier_ok(priv->dev))
7026 if (!stmmac_xdp_is_enabled(priv))
7029 if (queue >= priv->plat->rx_queues_to_use ||
7030 queue >= priv->plat->tx_queues_to_use)
7033 rx_q = &priv->dma_conf.rx_queue[queue];
7034 tx_q = &priv->dma_conf.tx_queue[queue];
7035 ch = &priv->channel[queue];
7037 if (!rx_q->xsk_pool && !tx_q->xsk_pool)
7040 if (!napi_if_scheduled_mark_missed(&ch->rxtx_napi)) {
7041 /* EQoS does not have per-DMA channel SW interrupt,
7042 * so we schedule RX Napi straight-away.
7044 if (likely(napi_schedule_prep(&ch->rxtx_napi)))
7045 __napi_schedule(&ch->rxtx_napi);
7051 static void stmmac_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7053 struct stmmac_priv *priv = netdev_priv(dev);
7054 u32 tx_cnt = priv->plat->tx_queues_to_use;
7055 u32 rx_cnt = priv->plat->rx_queues_to_use;
7059 for (q = 0; q < tx_cnt; q++) {
7060 struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[q];
7065 start = u64_stats_fetch_begin(&txq_stats->syncp);
7066 tx_packets = txq_stats->tx_packets;
7067 tx_bytes = txq_stats->tx_bytes;
7068 } while (u64_stats_fetch_retry(&txq_stats->syncp, start));
7070 stats->tx_packets += tx_packets;
7071 stats->tx_bytes += tx_bytes;
7074 for (q = 0; q < rx_cnt; q++) {
7075 struct stmmac_rxq_stats *rxq_stats = &priv->xstats.rxq_stats[q];
7080 start = u64_stats_fetch_begin(&rxq_stats->syncp);
7081 rx_packets = rxq_stats->rx_packets;
7082 rx_bytes = rxq_stats->rx_bytes;
7083 } while (u64_stats_fetch_retry(&rxq_stats->syncp, start));
7085 stats->rx_packets += rx_packets;
7086 stats->rx_bytes += rx_bytes;
7089 stats->rx_dropped = priv->xstats.rx_dropped;
7090 stats->rx_errors = priv->xstats.rx_errors;
7091 stats->tx_dropped = priv->xstats.tx_dropped;
7092 stats->tx_errors = priv->xstats.tx_errors;
7093 stats->tx_carrier_errors = priv->xstats.tx_losscarrier + priv->xstats.tx_carrier;
7094 stats->collisions = priv->xstats.tx_collision + priv->xstats.rx_collision;
7095 stats->rx_length_errors = priv->xstats.rx_length;
7096 stats->rx_crc_errors = priv->xstats.rx_crc_errors;
7097 stats->rx_over_errors = priv->xstats.rx_overflow_cntr;
7098 stats->rx_missed_errors = priv->xstats.rx_missed_cntr;
7101 static const struct net_device_ops stmmac_netdev_ops = {
7102 .ndo_open = stmmac_open,
7103 .ndo_start_xmit = stmmac_xmit,
7104 .ndo_stop = stmmac_release,
7105 .ndo_change_mtu = stmmac_change_mtu,
7106 .ndo_fix_features = stmmac_fix_features,
7107 .ndo_set_features = stmmac_set_features,
7108 .ndo_set_rx_mode = stmmac_set_rx_mode,
7109 .ndo_tx_timeout = stmmac_tx_timeout,
7110 .ndo_eth_ioctl = stmmac_ioctl,
7111 .ndo_get_stats64 = stmmac_get_stats64,
7112 .ndo_setup_tc = stmmac_setup_tc,
7113 .ndo_select_queue = stmmac_select_queue,
7114 .ndo_set_mac_address = stmmac_set_mac_address,
7115 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid,
7116 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid,
7117 .ndo_bpf = stmmac_bpf,
7118 .ndo_xdp_xmit = stmmac_xdp_xmit,
7119 .ndo_xsk_wakeup = stmmac_xsk_wakeup,
7122 static void stmmac_reset_subtask(struct stmmac_priv *priv)
7124 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state))
7126 if (test_bit(STMMAC_DOWN, &priv->state))
7129 netdev_err(priv->dev, "Reset adapter.\n");
7132 netif_trans_update(priv->dev);
7133 while (test_and_set_bit(STMMAC_RESETING, &priv->state))
7134 usleep_range(1000, 2000);
7136 set_bit(STMMAC_DOWN, &priv->state);
7137 dev_close(priv->dev);
7138 dev_open(priv->dev, NULL);
7139 clear_bit(STMMAC_DOWN, &priv->state);
7140 clear_bit(STMMAC_RESETING, &priv->state);
7144 static void stmmac_service_task(struct work_struct *work)
7146 struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
7149 stmmac_reset_subtask(priv);
7150 clear_bit(STMMAC_SERVICE_SCHED, &priv->state);
7154 * stmmac_hw_init - Init the MAC device
7155 * @priv: driver private structure
7156 * Description: this function is to configure the MAC device according to
7157 * some platform parameters or the HW capability register. It prepares the
7158 * driver to use either ring or chain modes and to setup either enhanced or
7159 * normal descriptors.
7161 static int stmmac_hw_init(struct stmmac_priv *priv)
7165 /* dwmac-sun8i only work in chain mode */
7166 if (priv->plat->flags & STMMAC_FLAG_HAS_SUN8I)
7168 priv->chain_mode = chain_mode;
7170 /* Initialize HW Interface */
7171 ret = stmmac_hwif_init(priv);
7175 /* Get the HW capability (new GMAC newer than 3.50a) */
7176 priv->hw_cap_support = stmmac_get_hw_features(priv);
7177 if (priv->hw_cap_support) {
7178 dev_info(priv->device, "DMA HW capability register supported\n");
7180 /* We can override some gmac/dma configuration fields: e.g.
7181 * enh_desc, tx_coe (e.g. that are passed through the
7182 * platform) with the values from the HW capability
7183 * register (if supported).
7185 priv->plat->enh_desc = priv->dma_cap.enh_desc;
7186 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up &&
7187 !(priv->plat->flags & STMMAC_FLAG_USE_PHY_WOL);
7188 priv->hw->pmt = priv->plat->pmt;
7189 if (priv->dma_cap.hash_tb_sz) {
7190 priv->hw->multicast_filter_bins =
7191 (BIT(priv->dma_cap.hash_tb_sz) << 5);
7192 priv->hw->mcast_bits_log2 =
7193 ilog2(priv->hw->multicast_filter_bins);
7196 /* TXCOE doesn't work in thresh DMA mode */
7197 if (priv->plat->force_thresh_dma_mode)
7198 priv->plat->tx_coe = 0;
7200 priv->plat->tx_coe = priv->dma_cap.tx_coe;
7202 /* In case of GMAC4 rx_coe is from HW cap register. */
7203 priv->plat->rx_coe = priv->dma_cap.rx_coe;
7205 if (priv->dma_cap.rx_coe_type2)
7206 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
7207 else if (priv->dma_cap.rx_coe_type1)
7208 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
7211 dev_info(priv->device, "No HW DMA feature register supported\n");
7214 if (priv->plat->rx_coe) {
7215 priv->hw->rx_csum = priv->plat->rx_coe;
7216 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
7217 if (priv->synopsys_id < DWMAC_CORE_4_00)
7218 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
7220 if (priv->plat->tx_coe)
7221 dev_info(priv->device, "TX Checksum insertion supported\n");
7223 if (priv->plat->pmt) {
7224 dev_info(priv->device, "Wake-Up On Lan supported\n");
7225 device_set_wakeup_capable(priv->device, 1);
7228 if (priv->dma_cap.tsoen)
7229 dev_info(priv->device, "TSO supported\n");
7231 priv->hw->vlan_fail_q_en =
7232 (priv->plat->flags & STMMAC_FLAG_VLAN_FAIL_Q_EN);
7233 priv->hw->vlan_fail_q = priv->plat->vlan_fail_q;
7235 /* Run HW quirks, if any */
7236 if (priv->hwif_quirks) {
7237 ret = priv->hwif_quirks(priv);
7242 /* Rx Watchdog is available in the COREs newer than the 3.40.
7243 * In some case, for example on bugged HW this feature
7244 * has to be disable and this can be done by passing the
7245 * riwt_off field from the platform.
7247 if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
7248 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
7250 dev_info(priv->device,
7251 "Enable RX Mitigation via HW Watchdog Timer\n");
7257 static void stmmac_napi_add(struct net_device *dev)
7259 struct stmmac_priv *priv = netdev_priv(dev);
7262 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
7264 for (queue = 0; queue < maxq; queue++) {
7265 struct stmmac_channel *ch = &priv->channel[queue];
7267 ch->priv_data = priv;
7269 spin_lock_init(&ch->lock);
7271 if (queue < priv->plat->rx_queues_to_use) {
7272 netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx);
7274 if (queue < priv->plat->tx_queues_to_use) {
7275 netif_napi_add_tx(dev, &ch->tx_napi,
7276 stmmac_napi_poll_tx);
7278 if (queue < priv->plat->rx_queues_to_use &&
7279 queue < priv->plat->tx_queues_to_use) {
7280 netif_napi_add(dev, &ch->rxtx_napi,
7281 stmmac_napi_poll_rxtx);
7286 static void stmmac_napi_del(struct net_device *dev)
7288 struct stmmac_priv *priv = netdev_priv(dev);
7291 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
7293 for (queue = 0; queue < maxq; queue++) {
7294 struct stmmac_channel *ch = &priv->channel[queue];
7296 if (queue < priv->plat->rx_queues_to_use)
7297 netif_napi_del(&ch->rx_napi);
7298 if (queue < priv->plat->tx_queues_to_use)
7299 netif_napi_del(&ch->tx_napi);
7300 if (queue < priv->plat->rx_queues_to_use &&
7301 queue < priv->plat->tx_queues_to_use) {
7302 netif_napi_del(&ch->rxtx_napi);
7307 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt)
7309 struct stmmac_priv *priv = netdev_priv(dev);
7312 if (netif_running(dev))
7313 stmmac_release(dev);
7315 stmmac_napi_del(dev);
7317 priv->plat->rx_queues_to_use = rx_cnt;
7318 priv->plat->tx_queues_to_use = tx_cnt;
7319 if (!netif_is_rxfh_configured(dev))
7320 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
7321 priv->rss.table[i] = ethtool_rxfh_indir_default(i,
7324 stmmac_set_half_duplex(priv);
7325 stmmac_napi_add(dev);
7327 if (netif_running(dev))
7328 ret = stmmac_open(dev);
7333 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size)
7335 struct stmmac_priv *priv = netdev_priv(dev);
7338 if (netif_running(dev))
7339 stmmac_release(dev);
7341 priv->dma_conf.dma_rx_size = rx_size;
7342 priv->dma_conf.dma_tx_size = tx_size;
7344 if (netif_running(dev))
7345 ret = stmmac_open(dev);
7350 #define SEND_VERIFY_MPAKCET_FMT "Send Verify mPacket lo_state=%d lp_state=%d\n"
7351 static void stmmac_fpe_lp_task(struct work_struct *work)
7353 struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
7355 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
7356 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
7357 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
7358 bool *hs_enable = &fpe_cfg->hs_enable;
7359 bool *enable = &fpe_cfg->enable;
7362 while (retries-- > 0) {
7363 /* Bail out immediately if FPE handshake is OFF */
7364 if (*lo_state == FPE_STATE_OFF || !*hs_enable)
7367 if (*lo_state == FPE_STATE_ENTERING_ON &&
7368 *lp_state == FPE_STATE_ENTERING_ON) {
7369 stmmac_fpe_configure(priv, priv->ioaddr,
7371 priv->plat->tx_queues_to_use,
7372 priv->plat->rx_queues_to_use,
7375 netdev_info(priv->dev, "configured FPE\n");
7377 *lo_state = FPE_STATE_ON;
7378 *lp_state = FPE_STATE_ON;
7379 netdev_info(priv->dev, "!!! BOTH FPE stations ON\n");
7383 if ((*lo_state == FPE_STATE_CAPABLE ||
7384 *lo_state == FPE_STATE_ENTERING_ON) &&
7385 *lp_state != FPE_STATE_ON) {
7386 netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT,
7387 *lo_state, *lp_state);
7388 stmmac_fpe_send_mpacket(priv, priv->ioaddr,
7392 /* Sleep then retry */
7396 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state);
7399 void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable)
7401 if (priv->plat->fpe_cfg->hs_enable != enable) {
7403 stmmac_fpe_send_mpacket(priv, priv->ioaddr,
7404 priv->plat->fpe_cfg,
7407 priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF;
7408 priv->plat->fpe_cfg->lp_fpe_state = FPE_STATE_OFF;
7411 priv->plat->fpe_cfg->hs_enable = enable;
7415 static int stmmac_xdp_rx_timestamp(const struct xdp_md *_ctx, u64 *timestamp)
7417 const struct stmmac_xdp_buff *ctx = (void *)_ctx;
7418 struct dma_desc *desc_contains_ts = ctx->desc;
7419 struct stmmac_priv *priv = ctx->priv;
7420 struct dma_desc *ndesc = ctx->ndesc;
7421 struct dma_desc *desc = ctx->desc;
7424 if (!priv->hwts_rx_en)
7427 /* For GMAC4, the valid timestamp is from CTX next desc. */
7428 if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
7429 desc_contains_ts = ndesc;
7431 /* Check if timestamp is available */
7432 if (stmmac_get_rx_timestamp_status(priv, desc, ndesc, priv->adv_ts)) {
7433 stmmac_get_timestamp(priv, desc_contains_ts, priv->adv_ts, &ns);
7434 ns -= priv->plat->cdc_error_adj;
7435 *timestamp = ns_to_ktime(ns);
7442 static const struct xdp_metadata_ops stmmac_xdp_metadata_ops = {
7443 .xmo_rx_timestamp = stmmac_xdp_rx_timestamp,
7448 * @device: device pointer
7449 * @plat_dat: platform data pointer
7450 * @res: stmmac resource pointer
7451 * Description: this is the main probe function used to
7452 * call the alloc_etherdev, allocate the priv structure.
7454 * returns 0 on success, otherwise errno.
7456 int stmmac_dvr_probe(struct device *device,
7457 struct plat_stmmacenet_data *plat_dat,
7458 struct stmmac_resources *res)
7460 struct net_device *ndev = NULL;
7461 struct stmmac_priv *priv;
7465 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv),
7466 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES);
7470 SET_NETDEV_DEV(ndev, device);
7472 priv = netdev_priv(ndev);
7473 priv->device = device;
7476 for (i = 0; i < MTL_MAX_RX_QUEUES; i++)
7477 u64_stats_init(&priv->xstats.rxq_stats[i].syncp);
7478 for (i = 0; i < MTL_MAX_TX_QUEUES; i++)
7479 u64_stats_init(&priv->xstats.txq_stats[i].syncp);
7481 stmmac_set_ethtool_ops(ndev);
7482 priv->pause = pause;
7483 priv->plat = plat_dat;
7484 priv->ioaddr = res->addr;
7485 priv->dev->base_addr = (unsigned long)res->addr;
7486 priv->plat->dma_cfg->multi_msi_en =
7487 (priv->plat->flags & STMMAC_FLAG_MULTI_MSI_EN);
7489 priv->dev->irq = res->irq;
7490 priv->wol_irq = res->wol_irq;
7491 priv->lpi_irq = res->lpi_irq;
7492 priv->sfty_ce_irq = res->sfty_ce_irq;
7493 priv->sfty_ue_irq = res->sfty_ue_irq;
7494 for (i = 0; i < MTL_MAX_RX_QUEUES; i++)
7495 priv->rx_irq[i] = res->rx_irq[i];
7496 for (i = 0; i < MTL_MAX_TX_QUEUES; i++)
7497 priv->tx_irq[i] = res->tx_irq[i];
7499 if (!is_zero_ether_addr(res->mac))
7500 eth_hw_addr_set(priv->dev, res->mac);
7502 dev_set_drvdata(device, priv->dev);
7504 /* Verify driver arguments */
7505 stmmac_verify_args();
7507 priv->af_xdp_zc_qps = bitmap_zalloc(MTL_MAX_TX_QUEUES, GFP_KERNEL);
7508 if (!priv->af_xdp_zc_qps)
7511 /* Allocate workqueue */
7512 priv->wq = create_singlethread_workqueue("stmmac_wq");
7514 dev_err(priv->device, "failed to create workqueue\n");
7519 INIT_WORK(&priv->service_task, stmmac_service_task);
7521 /* Initialize Link Partner FPE workqueue */
7522 INIT_WORK(&priv->fpe_task, stmmac_fpe_lp_task);
7524 /* Override with kernel parameters if supplied XXX CRS XXX
7525 * this needs to have multiple instances
7527 if ((phyaddr >= 0) && (phyaddr <= 31))
7528 priv->plat->phy_addr = phyaddr;
7530 if (priv->plat->stmmac_rst) {
7531 ret = reset_control_assert(priv->plat->stmmac_rst);
7532 reset_control_deassert(priv->plat->stmmac_rst);
7533 /* Some reset controllers have only reset callback instead of
7534 * assert + deassert callbacks pair.
7536 if (ret == -ENOTSUPP)
7537 reset_control_reset(priv->plat->stmmac_rst);
7540 ret = reset_control_deassert(priv->plat->stmmac_ahb_rst);
7541 if (ret == -ENOTSUPP)
7542 dev_err(priv->device, "unable to bring out of ahb reset: %pe\n",
7545 /* Init MAC and get the capabilities */
7546 ret = stmmac_hw_init(priv);
7550 /* Only DWMAC core version 5.20 onwards supports HW descriptor prefetch.
7552 if (priv->synopsys_id < DWMAC_CORE_5_20)
7553 priv->plat->dma_cfg->dche = false;
7555 stmmac_check_ether_addr(priv);
7557 ndev->netdev_ops = &stmmac_netdev_ops;
7559 ndev->xdp_metadata_ops = &stmmac_xdp_metadata_ops;
7560 ndev->xsk_tx_metadata_ops = &stmmac_xsk_tx_metadata_ops;
7562 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
7564 ndev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT |
7565 NETDEV_XDP_ACT_XSK_ZEROCOPY;
7567 ret = stmmac_tc_init(priv, priv);
7569 ndev->hw_features |= NETIF_F_HW_TC;
7572 if ((priv->plat->flags & STMMAC_FLAG_TSO_EN) && (priv->dma_cap.tsoen)) {
7573 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
7574 if (priv->plat->has_gmac4)
7575 ndev->hw_features |= NETIF_F_GSO_UDP_L4;
7577 dev_info(priv->device, "TSO feature enabled\n");
7580 if (priv->dma_cap.sphen &&
7581 !(priv->plat->flags & STMMAC_FLAG_SPH_DISABLE)) {
7582 ndev->hw_features |= NETIF_F_GRO;
7583 priv->sph_cap = true;
7584 priv->sph = priv->sph_cap;
7585 dev_info(priv->device, "SPH feature enabled\n");
7588 /* Ideally our host DMA address width is the same as for the
7589 * device. However, it may differ and then we have to use our
7590 * host DMA width for allocation and the device DMA width for
7591 * register handling.
7593 if (priv->plat->host_dma_width)
7594 priv->dma_cap.host_dma_width = priv->plat->host_dma_width;
7596 priv->dma_cap.host_dma_width = priv->dma_cap.addr64;
7598 if (priv->dma_cap.host_dma_width) {
7599 ret = dma_set_mask_and_coherent(device,
7600 DMA_BIT_MASK(priv->dma_cap.host_dma_width));
7602 dev_info(priv->device, "Using %d/%d bits DMA host/device width\n",
7603 priv->dma_cap.host_dma_width, priv->dma_cap.addr64);
7606 * If more than 32 bits can be addressed, make sure to
7607 * enable enhanced addressing mode.
7609 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
7610 priv->plat->dma_cfg->eame = true;
7612 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32));
7614 dev_err(priv->device, "Failed to set DMA Mask\n");
7618 priv->dma_cap.host_dma_width = 32;
7622 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
7623 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
7624 #ifdef STMMAC_VLAN_TAG_USED
7625 /* Both mac100 and gmac support receive VLAN tag detection */
7626 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
7627 ndev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
7628 priv->hw->hw_vlan_en = true;
7630 if (priv->dma_cap.vlhash) {
7631 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
7632 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
7634 if (priv->dma_cap.vlins) {
7635 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX;
7636 if (priv->dma_cap.dvlan)
7637 ndev->features |= NETIF_F_HW_VLAN_STAG_TX;
7640 priv->msg_enable = netif_msg_init(debug, default_msg_level);
7642 priv->xstats.threshold = tc;
7644 /* Initialize RSS */
7645 rxq = priv->plat->rx_queues_to_use;
7646 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key));
7647 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
7648 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq);
7650 if (priv->dma_cap.rssen && priv->plat->rss_en)
7651 ndev->features |= NETIF_F_RXHASH;
7653 ndev->vlan_features |= ndev->features;
7654 /* TSO doesn't work on VLANs yet */
7655 ndev->vlan_features &= ~NETIF_F_TSO;
7657 /* MTU range: 46 - hw-specific max */
7658 ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
7659 if (priv->plat->has_xgmac)
7660 ndev->max_mtu = XGMAC_JUMBO_LEN;
7661 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
7662 ndev->max_mtu = JUMBO_LEN;
7664 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
7665 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
7666 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
7668 if ((priv->plat->maxmtu < ndev->max_mtu) &&
7669 (priv->plat->maxmtu >= ndev->min_mtu))
7670 ndev->max_mtu = priv->plat->maxmtu;
7671 else if (priv->plat->maxmtu < ndev->min_mtu)
7672 dev_warn(priv->device,
7673 "%s: warning: maxmtu having invalid value (%d)\n",
7674 __func__, priv->plat->maxmtu);
7677 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
7679 ndev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7681 /* Setup channels NAPI */
7682 stmmac_napi_add(ndev);
7684 mutex_init(&priv->lock);
7686 /* If a specific clk_csr value is passed from the platform
7687 * this means that the CSR Clock Range selection cannot be
7688 * changed at run-time and it is fixed. Viceversa the driver'll try to
7689 * set the MDC clock dynamically according to the csr actual
7692 if (priv->plat->clk_csr >= 0)
7693 priv->clk_csr = priv->plat->clk_csr;
7695 stmmac_clk_csr_set(priv);
7697 stmmac_check_pcs_mode(priv);
7699 pm_runtime_get_noresume(device);
7700 pm_runtime_set_active(device);
7701 if (!pm_runtime_enabled(device))
7702 pm_runtime_enable(device);
7704 if (priv->hw->pcs != STMMAC_PCS_TBI &&
7705 priv->hw->pcs != STMMAC_PCS_RTBI) {
7706 /* MDIO bus Registration */
7707 ret = stmmac_mdio_register(ndev);
7709 dev_err_probe(priv->device, ret,
7710 "%s: MDIO bus (id: %d) registration failed\n",
7711 __func__, priv->plat->bus_id);
7712 goto error_mdio_register;
7716 if (priv->plat->speed_mode_2500)
7717 priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv);
7719 if (priv->plat->mdio_bus_data && priv->plat->mdio_bus_data->has_xpcs) {
7720 ret = stmmac_xpcs_setup(priv->mii);
7722 goto error_xpcs_setup;
7725 ret = stmmac_phy_setup(priv);
7727 netdev_err(ndev, "failed to setup phy (%d)\n", ret);
7728 goto error_phy_setup;
7731 ret = register_netdev(ndev);
7733 dev_err(priv->device, "%s: ERROR %i registering the device\n",
7735 goto error_netdev_register;
7738 #ifdef CONFIG_DEBUG_FS
7739 stmmac_init_fs(ndev);
7742 if (priv->plat->dump_debug_regs)
7743 priv->plat->dump_debug_regs(priv->plat->bsp_priv);
7745 /* Let pm_runtime_put() disable the clocks.
7746 * If CONFIG_PM is not enabled, the clocks will stay powered.
7748 pm_runtime_put(device);
7752 error_netdev_register:
7753 phylink_destroy(priv->phylink);
7756 if (priv->hw->pcs != STMMAC_PCS_TBI &&
7757 priv->hw->pcs != STMMAC_PCS_RTBI)
7758 stmmac_mdio_unregister(ndev);
7759 error_mdio_register:
7760 stmmac_napi_del(ndev);
7762 destroy_workqueue(priv->wq);
7764 bitmap_free(priv->af_xdp_zc_qps);
7768 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
7772 * @dev: device pointer
7773 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
7774 * changes the link status, releases the DMA descriptor rings.
7776 void stmmac_dvr_remove(struct device *dev)
7778 struct net_device *ndev = dev_get_drvdata(dev);
7779 struct stmmac_priv *priv = netdev_priv(ndev);
7781 netdev_info(priv->dev, "%s: removing driver", __func__);
7783 pm_runtime_get_sync(dev);
7785 stmmac_stop_all_dma(priv);
7786 stmmac_mac_set(priv, priv->ioaddr, false);
7787 netif_carrier_off(ndev);
7788 unregister_netdev(ndev);
7790 #ifdef CONFIG_DEBUG_FS
7791 stmmac_exit_fs(ndev);
7793 phylink_destroy(priv->phylink);
7794 if (priv->plat->stmmac_rst)
7795 reset_control_assert(priv->plat->stmmac_rst);
7796 reset_control_assert(priv->plat->stmmac_ahb_rst);
7797 if (priv->hw->pcs != STMMAC_PCS_TBI &&
7798 priv->hw->pcs != STMMAC_PCS_RTBI)
7799 stmmac_mdio_unregister(ndev);
7800 destroy_workqueue(priv->wq);
7801 mutex_destroy(&priv->lock);
7802 bitmap_free(priv->af_xdp_zc_qps);
7804 pm_runtime_disable(dev);
7805 pm_runtime_put_noidle(dev);
7807 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
7810 * stmmac_suspend - suspend callback
7811 * @dev: device pointer
7812 * Description: this is the function to suspend the device and it is called
7813 * by the platform driver to stop the network queue, release the resources,
7814 * program the PMT register (for WoL), clean and release driver resources.
7816 int stmmac_suspend(struct device *dev)
7818 struct net_device *ndev = dev_get_drvdata(dev);
7819 struct stmmac_priv *priv = netdev_priv(ndev);
7822 if (!ndev || !netif_running(ndev))
7825 mutex_lock(&priv->lock);
7827 netif_device_detach(ndev);
7829 stmmac_disable_all_queues(priv);
7831 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
7832 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer);
7834 if (priv->eee_enabled) {
7835 priv->tx_path_in_lpi_mode = false;
7836 del_timer_sync(&priv->eee_ctrl_timer);
7839 /* Stop TX/RX DMA */
7840 stmmac_stop_all_dma(priv);
7842 if (priv->plat->serdes_powerdown)
7843 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv);
7845 /* Enable Power down mode by programming the PMT regs */
7846 if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7847 stmmac_pmt(priv, priv->hw, priv->wolopts);
7850 stmmac_mac_set(priv, priv->ioaddr, false);
7851 pinctrl_pm_select_sleep_state(priv->device);
7854 mutex_unlock(&priv->lock);
7857 if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7858 phylink_suspend(priv->phylink, true);
7860 if (device_may_wakeup(priv->device))
7861 phylink_speed_down(priv->phylink, false);
7862 phylink_suspend(priv->phylink, false);
7866 if (priv->dma_cap.fpesel) {
7868 stmmac_fpe_configure(priv, priv->ioaddr,
7869 priv->plat->fpe_cfg,
7870 priv->plat->tx_queues_to_use,
7871 priv->plat->rx_queues_to_use, false);
7873 stmmac_fpe_handshake(priv, false);
7874 stmmac_fpe_stop_wq(priv);
7877 priv->speed = SPEED_UNKNOWN;
7880 EXPORT_SYMBOL_GPL(stmmac_suspend);
7882 static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue)
7884 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
7890 static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue)
7892 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
7898 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
7902 * stmmac_reset_queues_param - reset queue parameters
7903 * @priv: device pointer
7905 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
7907 u32 rx_cnt = priv->plat->rx_queues_to_use;
7908 u32 tx_cnt = priv->plat->tx_queues_to_use;
7911 for (queue = 0; queue < rx_cnt; queue++)
7912 stmmac_reset_rx_queue(priv, queue);
7914 for (queue = 0; queue < tx_cnt; queue++)
7915 stmmac_reset_tx_queue(priv, queue);
7919 * stmmac_resume - resume callback
7920 * @dev: device pointer
7921 * Description: when resume this function is invoked to setup the DMA and CORE
7922 * in a usable state.
7924 int stmmac_resume(struct device *dev)
7926 struct net_device *ndev = dev_get_drvdata(dev);
7927 struct stmmac_priv *priv = netdev_priv(ndev);
7930 if (!netif_running(ndev))
7933 /* Power Down bit, into the PM register, is cleared
7934 * automatically as soon as a magic packet or a Wake-up frame
7935 * is received. Anyway, it's better to manually clear
7936 * this bit because it can generate problems while resuming
7937 * from another devices (e.g. serial console).
7939 if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7940 mutex_lock(&priv->lock);
7941 stmmac_pmt(priv, priv->hw, 0);
7942 mutex_unlock(&priv->lock);
7945 pinctrl_pm_select_default_state(priv->device);
7946 /* reset the phy so that it's ready */
7948 stmmac_mdio_reset(priv->mii);
7951 if (!(priv->plat->flags & STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP) &&
7952 priv->plat->serdes_powerup) {
7953 ret = priv->plat->serdes_powerup(ndev,
7954 priv->plat->bsp_priv);
7961 if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7962 phylink_resume(priv->phylink);
7964 phylink_resume(priv->phylink);
7965 if (device_may_wakeup(priv->device))
7966 phylink_speed_up(priv->phylink);
7971 mutex_lock(&priv->lock);
7973 stmmac_reset_queues_param(priv);
7975 stmmac_free_tx_skbufs(priv);
7976 stmmac_clear_descriptors(priv, &priv->dma_conf);
7978 stmmac_hw_setup(ndev, false);
7979 stmmac_init_coalesce(priv);
7980 stmmac_set_rx_mode(ndev);
7982 stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw);
7984 stmmac_enable_all_queues(priv);
7985 stmmac_enable_all_dma_irq(priv);
7987 mutex_unlock(&priv->lock);
7990 netif_device_attach(ndev);
7994 EXPORT_SYMBOL_GPL(stmmac_resume);
7997 static int __init stmmac_cmdline_opt(char *str)
8003 while ((opt = strsep(&str, ",")) != NULL) {
8004 if (!strncmp(opt, "debug:", 6)) {
8005 if (kstrtoint(opt + 6, 0, &debug))
8007 } else if (!strncmp(opt, "phyaddr:", 8)) {
8008 if (kstrtoint(opt + 8, 0, &phyaddr))
8010 } else if (!strncmp(opt, "buf_sz:", 7)) {
8011 if (kstrtoint(opt + 7, 0, &buf_sz))
8013 } else if (!strncmp(opt, "tc:", 3)) {
8014 if (kstrtoint(opt + 3, 0, &tc))
8016 } else if (!strncmp(opt, "watchdog:", 9)) {
8017 if (kstrtoint(opt + 9, 0, &watchdog))
8019 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
8020 if (kstrtoint(opt + 10, 0, &flow_ctrl))
8022 } else if (!strncmp(opt, "pause:", 6)) {
8023 if (kstrtoint(opt + 6, 0, &pause))
8025 } else if (!strncmp(opt, "eee_timer:", 10)) {
8026 if (kstrtoint(opt + 10, 0, &eee_timer))
8028 } else if (!strncmp(opt, "chain_mode:", 11)) {
8029 if (kstrtoint(opt + 11, 0, &chain_mode))
8036 pr_err("%s: ERROR broken module parameter conversion", __func__);
8040 __setup("stmmaceth=", stmmac_cmdline_opt);
8043 static int __init stmmac_init(void)
8045 #ifdef CONFIG_DEBUG_FS
8046 /* Create debugfs main directory if it doesn't exist yet */
8048 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
8049 register_netdevice_notifier(&stmmac_notifier);
8055 static void __exit stmmac_exit(void)
8057 #ifdef CONFIG_DEBUG_FS
8058 unregister_netdevice_notifier(&stmmac_notifier);
8059 debugfs_remove_recursive(stmmac_fs_dir);
8063 module_init(stmmac_init)
8064 module_exit(stmmac_exit)
8066 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
8067 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
8068 MODULE_LICENSE("GPL");